用于先进PCB制造工艺的叠层封装

在20世纪90年代,球栅阵列封装(BGA)和芯片尺寸封装(CSP)在封装材料和加工工艺方面达到了极限。这2种技术如同20世纪80年代的表面安装器件(SMD)和70年代通孔安装器件(THD)一样,在电学、机械、热性能、尺寸、质量和可靠性方面达到最大值。目前,三维封装正在成为用于未来采用的先进印制板(PCB)制造工艺的下一个阶段。它们可以分为圆片级封装、芯片级封装、和封装面。叠层封装(PoP)是一种封装面叠层封装类型的三维封装技术[15]。     

A Novel and Efficient Feature Extraction Method for Iris Recognition

With a growing emphasis on human identification, iris recognition has recently received increasing attention. Iris recognition includes eye imaging, iris segmentation, verification, and so on. In this letter, we propose a novel and efficient iris recognition method which employs a cumulative‐sum‐based grey change analysis. Experimental results demonstrate that the proposed method can be used for human identification in efficient manner.     

Metal Organic Framework-MXene Nanoarchitecture for Fast Responsive and Ultra-Stable Electro-Ionic Artificial Muscles

Electro-ionic soft actuators, capable of continuous deformations replacing non-compliant rigid mechanical components, attract increasing interest in the field of next-generation metaverse interfaces and soft robotics. Here, a novel MXene (Ti₃C₂T_x) electrode anchoring manganese-based 1,3,5-benzenetricarboxylate metal-organic framework (MnBTC) for ultrastable electro-ionic artificial muscles is reported. By a facile supramolecular self-assembly, the Ti₃C₂T_x-MnBTC hybrid nanoarchitecture forms coordinate bond, hydrogen bond, and hydrophilic interaction with the conducting polymer of poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), resulting in a mechanically flexible and electro-ionically active electrode. The superior electrical and electrochemical performances of the electrode stem from the synergistic effects between intrinsically hierarchical nanoarchitecture of MnBTC and rapid electron transport behavior of Mxene, leading to fast diffusion and accommodation of ions in the ion-exchangeable membrane. The developed artificial muscle based on Ti₃C₂T_x-MnBTC is found to exhibit high bending displacement (12.5 mm) and ultrafast response time (0.77 s) under a low driving voltage (0.5 V), along with wide frequency response (0.1–10 Hz) and exceptional stability (98% retention at 43,200 s) without any distortion of actuation performance. Furthermore, the designed electro-active artificial muscle is successfully used to demonstrate mimicry of eye motions including eyelid blinking and eyeball movement in a doll.     

A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-μm CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation     

Data Clustering Method Using a Modified Gaussian Kernel Metric and Kernel PCA

Most hyper‐ellipsoidal clustering (HEC) approaches use the Mahalanobis distance as a distance metric. It has been proven that HEC, under this condition, cannot be realized since the cost function of partitional clustering is a constant. We demonstrate that HEC with a modified Gaussian kernel metric can be interpreted as a problem of finding condensed ellipsoidal clusters (with respect to the volumes and densities of the clusters) and propose a practical HEC algorithm that is able to efficiently handle clusters that are ellipsoidal in shape and that are of different size and density. We then try to refine the HEC algorithm by utilizing ellipsoids defined on the kernel feature space to deal with more complex‐shaped clusters. The proposed methods lead to a significant improvement in the clustering results over K‐means algorithm, fuzzy C‐means algorithm, GMM‐EM algorithm, and HEC algorithm based on minimum‐volume ellipsoids using Mahalanobis distance.     

Growth of InGaN HBTs by MOCVD

The design and growth of GaN/InGaN heterojunction bipolar transistors (HBTs) by metalorganic chemical vapor deposition (MOCVD) are studied. Atomic-force microscopy (AFM) images of p⁺InGaN base layers (∼100 nm) deposited under various growth conditions indicate that the optimal growth temperature is limited to the range between 810 and 830°C due to a trade-off between surface roughness and indium incorporation. At these temperatures, the growth pressure must be kept above 300 Torr in order to keep surface pit density under control. An InGaN graded-composition emitter is adopted in order to reduce the number of V-shaped defects, which appear at the interface between GaN emitter and InGaN base and render an abrupt emitter-base heterojunction nearly impossible. However, the device performance is severely limited by the high p-type base contact resistance due to surface etching damage, which resulted from the emitter mesa etch.     

Dynamic control plane management for software‐defined networks

Software‐defined network (SDN) is an emerging network paradigm that allows flexible network management by providing programmability from a separated control plane. Because of the centralized management scheme that SDN adopts, intensive control plane overhead incurs as the scale of SDN increases. The control plane overhead is mainly caused by a massive amount of control messages generated during data plane monitoring and reactive flow instantiation. By far, very few works have addressed the overhead issue on reaction flow instantiation; therefore, we mainly focus on alleviating such overhead in this work. To achieve this goal, we propose a new control plane management (CPMan) method. CPMan aims to realize the following two objectives: first, reduce the number of control messages exchanged through the control channel and second, evenly distribute the control workload across multiple controllers to mitigate the potential performance bottleneck. To realize the former, we propose a lightweight feedback loop‐based control scheme, whereas for the latter, we propose a dynamic switch‐to‐controller (DSC) placement scheme. To show the feasibility of our proposal, we implemented a prototype of the two proposed schemes on top of a carrier‐grade SDN controller and validated its performance in an emulated network. We achieved approximately 57.13% overhead reduction with feedback loop‐based control scheme, while achieved approximately 98.68% balance ratio with DSC placement scheme. Copyright © 2016 John Wiley & Sons, Ltd.     

Compact 2.5 Gb/s Burst‐Mode Receiver with Optimum APD Gain for XG‐PON1 and GPON Applications

This letter presents a compact 2.5 Gb/s burst‐mode receiver using the first reported monolithic amplifier IC developed with 0.25 …m SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next‐generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.     

Monolithic arrays of surface emitting laser NOR logic devices

Monolithic, cascadable, laser-logic-device arrays have been realized and characterized. The monolithic surface-emitting laser logic (SELL) device consists of an AlGaAs superlattice lasing around 780 nm connected to a heterojunction phototransistor (HPT) in parallel and a resistor in series. Arrays up to 8×8 have been fabricated, and 2×2 arrays show uniform characteristics. The optical logic output is switched off with 40 μW incident optical input     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation