工程应用中不同包层直径光栅的结构选择与参数设计

使一个光纤光栅的两段分别具有不同的包层直径,在正确的应用条件下可解决工程中的应变、温度交叉敏感难题.对不同包层直径光栅在有、无涂覆层两种情况下的应交传感特性进行了深入的力学分析,推导得出了结构实际应变与两段光栅相对波长变化的关系表达式,并数值仿真分析了直径比和长度比对其应交灵敏特性的影响.研究结果有利于指导实际应用时光栅的结构选择和参数设计.此外指出,在实际工程应用中无论采用何种封装形式或复合方式,要从应变、温度的混合信息中提取出结构体的真实应变,必须使不同包层直径光栅满足两端拉伸的受力条件.     

菘蓝幼苗对激光和增强UV-B辐射的生理响应研究

以菘蓝(Isatis indigotica)为实验材料,研究了He-Ne激光和增强UV-B辐射对菘蓝幼苗抗氧化系统的影响.结果表明:与对照相比,激光处理提高了SOD,CAT和POD酶活性,降低了MDA含量,UV-B辐射降低了SOD,CAT和POD酶活性,提高了MDA含量,而UV-B辐射后再进行激光辐照使上述参数得到了不同程度的恢复;与对照相比,激光、UV-B辐射和UV-B与激光复合辐射导致紫外吸收物提高,其效果依次为激光与UV-B作用>UV-B>激光.论文在此基础上讨论了其可能的形成机理.     

钛锆对激光熔覆原位合成颗粒增强铁基复合涂层组织的影响

运用激光熔覆的方法在中碳钢表面原位合成制备了颗粒增强铁基复合涂层.通过调整两种强碳化物形成元素Ti和Zr的相对含量,研究了不同配比下原位自生碳化物颗粒相的分布特征.结果表明,在总量一定的情况下,复合添加Ti和Zr可以提高颗粒分布密度和颗粒相面积比.其中,以Ti和Zr的质量比为1∶1时得到的颗粒密度最大、颗粒尺寸分布最均匀.同时对不同的颗粒分布状态下涂层的显微硬度进行了研究.     

Nanoparticles of the Lead-free Solder Alloy Sn-3.0Ag-0.5Cu with Large Melting Temperature Depression

Due to the toxicity of lead (Pb), Pb-containing solder alloys are being phased out from the electronics industry. This has lead to the development and implementation of lead-free solders. Being an environmentally compatible material, the lead-free Sn-3.0Ag-0.5Cu (wt.%) solder alloy is considered to be one of the most promising alternatives to replace the traditionally used Sn-Pb solders. This alloy composition possesses, however, some weaknesses, mainly as a result of its higher melting temperature compared with the Sn-Pb solders. A possible way to decrease the melting temperature of a solder alloy is to decrease the alloy particle size down to the nanometer range. The melting temperature of Sn-3.0Ag-0.5Cu lead-free solder alloy, both as bulk and nanoparticles, was investigated. The nanoparticles were manufactured using the self-developed consumable-electrode direct current arc (CDCA) technique. The melting temperature of the nanoparticles, with an average size of 30 nm, was found to be 213.9°C, which is approximately 10°C lower than that of the bulk alloy. The developed CDCA technique is therefore a promising method to manufacture nanometer-sized solder alloy particles with lower melting temperature compared with the bulk alloy.     

稳健的高效MIMO检测器

无偏最小均方误差迭代树搜索(MMSE-ITS)检测器是目前性能最好的多输入多输出(MIMO)检测器之一。该文通过选择性地扩展部分长度路径和添加一位互补矢量,对无偏MMSE-ITS检测器作了改进。仿真和分析结果表明,和无偏MMSE-ITS检测算法相比,改进算法能以相对较低的处理复杂度获得更好的检测性能。另外,改进的检测器彻底避免了削剪处理,对MIMO信道状况具有较好的适应性,稳健性较强。     

一种基于IoT控制的小区间功率控制方法

该文针对OFDMA蜂窝系统中上行干扰特性,提出了基于IoT控制的小区间功率控制方法。该方法通过相邻小区相互交换干扰信息,对传统的功率控制进行修正,并根据调整原则和调整步长,提出了4种控制方法,使得系统IoT更稳定,吞吐量更高。仿真证实了这4种控制方法都优于传统未加IoT控制的功率控制方法,其中基于固定比较对象的自适应调整步长的功率控制方法最优。     

考虑工艺波动影响的RLC互连统计延时

该文提出了一种考虑工艺波动的统计RLC互连延时分析方法。文中首先给出了考虑工艺波动的寄生参数和矩的构建方法,然后基于Weibull分布给出了RLC互连的统计延时模型。所提方法同样适用于已有的延时模型如Elmore模型,等效Elmore模型和D2M模型。通过对几种模型的比较,表明,基于Weibull分布的RLC互连的统计延时模型是最精确的,和HSPICE相比,50%延时误差最大0.11%,蒙特卡洛分析中的均值和平均偏差误差最大2.02%。     

Effects of Ball-Milling Atmosphere on the Thermoelectric Properties of TAGS-85 Compounds

Inspired by the high ZT value lately attained in Ar-protected ball-milled nanocrystalline p-BiSbTe bulk alloy, we report herein an investigation of the effects of ball-milling atmosphere on the thermoelectric (TE) properties of the traditional TE material (GeTe)₈₅(AgSbTe₂)₁₅ (TAGS-85). TAGS-85 samples were prepared via a melting–quenching–annealing process, and then ball-milled in different atmospheres and subsequently densified using a spark plasma sintering technique. The Seebeck coefficient, electrical conductivity, thermal conductivity, and Hall coefficient were measured as a function of temperature from 10 K to 310 K. It was found that different ball-milling atmospheres, i.e., air, liquid N₂ (LN₂), and Ar, profoundly affected the TE properties. A state-of-the-art figure of merit ZT ≈ 0.30 was attained at 310 K in the Ar-ball milled sample. The results are discussed in terms of the carrier concentration, mobility, crystallinity, and the grain boundary scattering.     

汽车电压调节器集成电路芯片版图设计

介绍了基于4μm双极型对通隔离工艺的汽车电压调节器功率集成电路芯片的版图设计。版图设计的主要出发点是高精度、大调整电流和高可靠性三方面。版图中各模块采用了热对称设计和等温线设计,关键元件的匹配采用了中心对称设计,大功率调整管采用了宽发射极窄接触条和圣诞树型结构相结合的方案。芯片测试结果表明,电压调节器的调节精度为14.2±0.15V,最大调节电流为5A,较好地实现了预定电路功能。芯片成品率达80%。     

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.