Efficient visualization of large routing topologies

As the Internet grows in size and complexity, network managers face a significant challenge in trying to understand the behaviour of routing protocols in large networks. In this paper, we present a tool called VLNT (visualizing large network topologies), which helps network managers to analyse complex routing topologies. A key contribution of our system is a novel hybrid layout algorithm, which significantly reduces the computation time required to layout large network topologies in comparison to conventional layout approaches. In addition our algorithm includes a novel termination criterion that avoids unnecessary iterations when optimizing the network layout. We demonstrate how the visualization features of VLNT can be used to analyse and improve BGP routing topologies, and provide examples using real‐life routing data. Copyright © 2004 John Wiley & Sons, Ltd.     

Gain-enhanced compact broadband microstrip antenna

With the loading of a high-permittivity superstrate layer and a 1 Ω chip resistor, a compact rectangular microstrip antenna with enhanced gain and wider bandwidth can be implemented. With the antenna size reduced to be ~6% that of a conventional patch antenna, the proposed structure can have an operating bandwidth of more than six times that of a conventional patch antenna, with an almost equal antenna gain level. Details of the experimental results are presented and discussed     

Modified planar inverted F antenna

The design of a modified planar inverted F antenna (PIFA) which is more compact (antenna length <λ₀/8 and antenna height <0.01 λ₀) and has a much wider antenna bandwidth (greater than 10 times that of a simple PIFA) is demonstrated. The reduction in antenna length is achieved by meandering the radiating patch, while the enhanced bandwidth with low antenna height is obtained using a chip-resistor load in place of the shorting post. A typical design of the modified PIFA in the 800 MHz band has been implemented, and experimental results are presented and discussed     

Single-feed dual-band circularly polarised microstrip antenna

A novel technique for obtaining dual-band circular polarisation (CP) radiation of a single-feed circular microstrip antenna is proposed and demonstrated. By embedding two pairs of arc-shaped slots of proper lengths close to the boundary of a circular patch, and protruding one of the arc-shaped slots with a narrow slot, the circular microstrip antenna can perform dual-band CP radiation using a single probe feed. Details of the antenna design and experimental results are presented     

Small slot-coupled circularly-polarised microstrip antenna withmodified cross-slot and bent tuning-stub

A novel design of small slot-coupled circularly-polarised circular microstrip antenna with a modified cross-slot cut in the patch and a bent tuning-stub aligned along the patch boundary is proposed and experimentally studied. Results show that, for fixed circular polarisation (CP) operation, the antenna proposed can have an antenna size reduction of ~80%, as compared to a regular-size CP design. The significant size reduction of the proposed antenna is due to the novel modified cross-slot cut in the patch, and CP operation is obtained using a bent tuning-stub incorporating a properly oriented coupling-slot in the ground plane of the microstrip feed line     

Circularly polarised microstrip antenna with a tuning stub

A simple circular polarisation (CP) design of microstrip antennas using a tuning stub is proposed and studied. It is also demonstrated that, by applying this CP design method to a circular microstrip patch with a cross slot having equal slot lengths, a compact circularly-polarised microstrip antenna can easily be implemented, with much more relaxed manufacturing tolerances as compared to the case of using a cross slot of unequal slot lengths. Details of the antenna designs are described, and experimental results are presented and discussed     

Bandwidth enhancement of inset-microstrip-line-fedequilateral-triangular microstrip antenna

By embedding a pair of properly-bent narrow slots in an equilateral-triangular microstrip patch, broadband operation of microstrip antennas with an inset microstrip-line feed can be achieved. With the proposed antenna design, the impedance bandwidth can be as large as ~3.0 times that of a corresponding simple triangular microstrip antenna. Some simple design rules for the proposed antenna have also been determined experimentally. The design rules and experimental results are presented and discussed     

A study of tilt angle effect on Halo PMOS performance

The Halo structure is usually adopted in deep submicrometer MOS devices for punchthrough prevention. The tilt angle of the Halo implant determines the dopant distribution which induces anti-punchthrough operation. In this paper, we investigate the impact of the tilt angle on the Halo PMOS device performance via two-dimensional (2D) simulations. We find that the ratio of on-current to off-current is constant for all tilt angles of Halo implant, implying an equivalent DC performance for all tilt angles. The equivalence can be traced back to a self compensation between the body factor and source resistance. The result implies that a low tilt angle should be adopted for Halo devices, for it gives a small threshold voltage and thus a high noise margin. The methodology used in analyzing body factor and source resistance can also be applied to analyze other devices.     

A phenomenon of charge trapping saturation induced by rapid thermal annealing

In this paper, we investigate the impact of the rapid thermal annealing (RTA) temperature on the performance degradation of NMOS devices, due to hot electrons. Our results indicate that RTA with a higher temperature achieves a higher interface barrier and induces a greater initial positive trapped charge. We observe a new three-section degradation phenomenon during DC stress at a low RTA temperature of 875°C, along with the discovery of a non-monotonic substrate current degradation which finally saturates. We note that the non-monotonicity is induced by a trapped charge polarity change, and the saturation is induced by a progression of an injected charge pocket toward the channel. This study provides an insight into the analysis of device degradation vs the RTA temperature, and should be useful for reliability optimization in process integration.     

Simultaneous area and delay minimum K-LUT mapping for K-exact networks

We address the technology mapping problem for lookup table FPGAs. The area minimization problem, for mapping K-bounded networks, consisting of nodes with at most K inputs, using K-input lookup tables, is known to be NP-complete for K 5. The complexity was unknown for K = 2, 3, and 4. The corresponding delay minimization problem (under the constant delay model) was solved in polynomial time by the flow-map algorithm, for arbitrary values of K. We study the class of K-bounded networks, where all nodes have exactly K inputs. We call such networks K-exact. We give a characterization of mapping solutions for such networks. This leads to a polynomial time algorithm for computing the simultaneous area and delay minimum mapping for such networks using K-input lookup tables. We also show that the flow-map algorithm computes the same mapping solution as our algorithm. We then show that for K = 2 the mapping solution for a 2-bounded network, minimizing the area and delay simultaneously, can be easily obtained from that of a 2-exact network derived from it by eliminating single input nodes. Thus the area minimization problem for 2-input lookup tables can be solved in polynomial time, resolving an open problem.