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101.
102.
To confine guided light tightly in a small size with acceptable loss, recently a nanometre-size slot waveguide has been demonstrated experimentally [1]. Such a slot waveguide has two high-index regions (e.g. Si), between which there is a narrow slot region. This narrow slot usually has a width of about 100 nm (or less) and is filled by a low-index-material (e.g. air or SiO/sub 2/) [1]. Because of the continuity of the normal displacement field (product of the permittivity and electric field) at the interface between the low-index slot and the high-index region, one obtains an enhanced electric field intensity in the lowindex slot. This effect makes this novel type of optical waveguide very attractive in many applications [2, 3], e.g. modulation, nonlinear effects, sensing etc. In addition, some extended structures, e.g. a horizontal slot waveguide [4], a multiple-slot waveguide [5], etc. have also been developed. 相似文献
103.
Paul S. Ho Guotao Wang Min Ding Jie-Hua Zhao Xiang Dai 《Microelectronics Reliability》2004,44(5):719-737
In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages. 相似文献
104.
105.
为进一步揭示硫系玻璃基掺Er3+微结构光纤作为中红外光纤放大器增益介质的可行性,数值求解了800 nm泵浦波长下Ga5Ge20Sb10S65硫系玻璃基掺Er3+微结构光纤中Er3+离子数速率方程和光功率传输方程组,理论研究了4.5μm波段中红外信号的放大特性。结果显示,Ga5Ge20Sb10S65硫系玻璃基掺Er3+微结构光纤具有较高的信号增益和很宽的增益谱。在50 cm光纤长度上,最大信号增益超过了40 dB,高于30 dB信号增益的放大带宽达到了280 nm(4 420~4 700 nm)。同时,进一步研究分析了4 500 nm波长信号增益与光纤长度、信号输入功率和泵浦功率的关系。研究表明,Ga5Ge20Sb10S65硫系玻璃基掺Er3+微结构光纤是一种理想的可应用于4.5μm波段中红外宽带放大器的增益介质。 相似文献
106.
View-based 3-D object retrieval and recognition has become popular in practice, e.g., in computer aided design. It is difficult to precisely estimate the distance between two objects represented by multiple views. Thus, current view-based 3-D object retrieval and recognition methods may not perform well. In this paper, we propose a hypergraph analysis approach to address this problem by avoiding the estimation of the distance between objects. In particular, we construct multiple hypergraphs for a set of 3-D objects based on their 2-D views. In these hypergraphs, each vertex is an object, and each edge is a cluster of views. Therefore, an edge connects multiple vertices. We define the weight of each edge based on the similarities between any two views within the cluster. Retrieval and recognition are performed based on the hypergraphs. Therefore, our method can explore the higher order relationship among objects and does not use the distance between objects. We conduct experiments on the National Taiwan University 3-D model dataset and the ETH 3-D object collection. Experimental results demonstrate the effectiveness of the proposed method by comparing with the state-of-the-art methods. 相似文献
107.
Charl J. Jafta Xiao-Guang Sun Hailong Lyu Hao Chen Bishnu P. Thapaliya William T. Heller Matthew J. Cuneo Richard T. Mayes Mariappan Parans Paranthaman Sheng Dai Craig A. Bridges 《Advanced functional materials》2021,31(23):2008708
The formation of the solid electrolyte interphase (SEI) in an ionic liquid electrolyte of 0.5 m lithium bis(fluorosulfonyl)imide (LiFSI) in 1-ethyl-3-methylimidazolium bis(fluorosulfonyl)imide at high cell voltages (1.7–1.9 V) is investigated in ordered mesoporous carbon (OMC) based Li metal cells using an operando small-angle neutron scattering (SANS) technique coupled with electrochemical impedance spectroscopy and ex situ X-ray photoelectron spectroscopy (XPS). It is demonstrated that discharging the OMC Li metal cells to ≈2 V and holding the cell voltage constant induces a rapid current increase with time, confirming extensive reduction and SEI formation. XPS analysis reveals that LiF is formed at open cell voltage (OCV), which is attributed to the carbenes generated at the lithium negative electrode because of its reaction with EMIm cation diffusing to and initiating the reaction with FSI− anions at the carbon positive electrode. It is confirmed that the chemical reaction at OCV and electrochemical reduction at high cell voltage of the FSI− anion plays a protective role against EMIm cation co-intercalation into the carbon positive electrode during the initial discharge. Operando SANS studies also suggest that slight differences occur in the surface composition and reaction mechanism as a function of cell voltage. 相似文献
108.
109.
Kakani V. Fa Foster Dai Jaeger R.C. 《Microwave and Wireless Components Letters, IEEE》2007,17(6):457-459
This letter presents a novel quadrature voltage controlled oscillator (QVCO) implemented in a 47-GHz SiGe BiCMOS technology. The QVCO is a serially coupled LC VCO that utilizes SiGe heterojunction bipolar transistors for oscillation and metal oxide semiconductor field effect transistors for coupling. The SiGe BiCMOS QVCO prototype achieves about 14.6% tuning range from 4.3 to 5GHz. The phase noise of the QVCO is measured as -114.3 dBc/Hz at 2-MHz offset. The 5-GHz QVCO core consumes 6-mA current from a 3.3-V power supply and occupies 0.88mm2 area 相似文献
110.