Development of a colon delivery capsule and the pharmacological activity of recombinant human granulocyte colony-stimulating factor (rhG-CSF) in beagle dogs

A peroral dosage form was examined to deliver recombinant human granulocyte colony-stimulating factor (rhG-CSF) to the colon in beagle dogs. A new gelatin capsule with its inside surface coated with ethylcellulose was prepared for this purpose. RhG-CSF was dissolved with propylene glycol and was filled in the capsule. Several kinds of ethylcellulose-gelatin capsules with an ethylcellulose layer of thickness 46 to 221 mm were used. The capsule was filled with propylene glycol solution containing fluorescein as an absorption marker, castor oil derivative and citric acid. The hardness of the capsule was tested after the gelatin layer was dissolved using a hardness tester and was dependent on the thickness of the ethylcellulose layer of the capsule. The time, Tmax, at which plasma fluorescein level reaches its maximum following oral administration of ethylcellulose capsules was used as a parameter for the in-vivo disintegration time of the ethylcellulose capsule into the colon. Capsules of thickness 84 mm with a Tmax of 4-6 h were filled with rhG-CSF solution containing fluorescein and were administered to dogs. After administration, blood samples were collected for 96 h and the blood total leucocyte (BTL) counts were measured as a pharmacological index of rhG-CSF. The maximum BTL count appeared at 10 h then gradually decreased and returned to its normal level at 48 h. These results suggest the usefulness of ethylcellulose capsules for the delivery of rhG-CSF to the colon and the possibility of a new oral rhG-CSF dosage form has been elucidated.     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

1-GHz-spaced 16-channel arrayed-waveguide grating for a wavelength reference standard in DWDM network systems

We fabricated a 1-GHz-spaced 16-channel arrayed-waveguide grating (AWG) by using a new AWG configuration where the path of each arrayed waveguide winds backward and forward across a 4-in diameter wafer without crossing any other waveguides. The ultra-narrow (< 1 GHz) and stable transmission bands of this AWG can be used to construct a wavelength reference standard covering the S, C, and L bands in the dense wavelength-division-multiplexing network systems whose frequency deviation is /spl plusmn/160 MHz.     

Measurement of phase and amplitude error distributions inarrayed-waveguide grating multi/demultiplexers based on dispersivewaveguide

We measured the phase and amplitude error distributions in InP-based arrayed-waveguide grating (AWG) multi/demultiplexers using Fourier transform spectroscopy with interferogram restoration. The interferogram restoration was used to reduce the effect of the group-velocity dispersion of the waveguide. It was based on a wavenumber scale transformation or a dispersion balance between two arms in the interferometer. We derived a criterion for choosing the appropriate restoration method by estimating the worst-case measurement error in the presence of second order dispersion. After selecting a method using the derived criterion, we obtained isolated fringe patterns, from which we were able to obtain the phase and amplitude distributions in 50 and 200 GHz AWGs. Using the obtained distributions, we examined the origin of the crosstalk and chromatic dispersion in InP-based AWGs. The results revealed that the main origin is phase error as found with SiO₂ -based AWGs     

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectionaldelay and an interbank shared redundancy scheme

This paper describes three circuit technologies indispensable for high-bandwidth multibank DRAM's. (1) A clock generator based on a bidirectional delay (BDD) eliminates the output skew. The BDD measures the cycle time as the quantity charged or discharged of an analog quantity, and replicates it in the next cycle. This achieves a 0.18-mm ², two-cycle-lock clock generator operating from 25 to 167 MHz with a 30-ps resolution. (2) A quad-coupled receiver eliminates the internal skew caused by the difference between a rise input and a fall input by 40%. (3) An interbank shared redundancy scheme (ISR) with a variable unit redundancy (VUR) efficiently increases yield in multibank DRAM's. The ISR allows redundancy match circuits to be shared with two or more banks. The VUR allows the number of units replaced to be variable. These circuit technologies achieved a 250-Mb/s/pin, 8-bank, 1-Gb double-data-rate synchronous DRAM     

A highly efficient two-stage Er3+-doped optical fiberamplifier employing an optical gate to effectively reduce ASE

Highly efficient amplification of ultrashort optical pulses is demonstrated with a two-stage Er³⁺-doped optical fiber amplifier that includes an optical gate to efficiently reduce amplified spontaneous emission (ASE) generated from the first Er³⁺-doped fiber. A gain of 49 dB, an amplified peak power 0f 105 W, and 1.05 nJ pulse energy are achieved for 2-Mb/s, 10-ps pulses at a total pumping power of 90 mW from 1.48-μm LDs     

High-Speed Time Switch Using GaAs LSI Technology

A high-speed time switch using GaAs LSI technology is discussed. A new high-speed time switch structure consisting primarily of shift registers is proposed. This structure requires relatively minimal hardware in designing LSI. As the first stage of study, a GaAs 4-channel time switch LSI is manufactured using this structure. Switching speed of the LSI is 2 Gbits/s and the power consumption 0.64 W/chip. Largecapacity switch configurations using this time switch are proposed. This high-speed time switch makes possible the time-division switching of such services as T.V. and high-definition T.V.