Conditions of formation and magnetic properties of tetragonal Fe14La2B

Tetragonal Fe₁₄La₂B (a = 0.883 nm, c = 1.236 nm)is stable below 860°C. At 25°C it has a magnetization approaching 1.1 T in a field of 2000 kA/m. Its anisotropy field is considerably lower than that of related Fe₁₄Nd₂B or Fe₁₄Pr₂B.     

Analysis and optimization of series-gated CML and ECL high-speedbipolar circuits

An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented. The analytical delay model accounts for all the device parasitics and the device sizes of the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay). A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model     

Load-line analysis of i.i.l.

A d.c. load-line analysis of i.i.l. structures is performed. Calculations are made of logic levels, noise margins and effective circuit parameters. Although the analysis is simple, it enhances the understanding of the circuit operation, and its predictions are in agreement with experiment and with more complicated analyses.     

Nonsaturated integrated injection logic

Conventional integrated-injection-logic structures suffer from strong saturation of the n?p?n transistors. This increases the storage time, and hence puts a limitation on the propagation delay of the structures. A current-control technique is given to reduce this effect without changing the basic i.i.l. structure.     

Base component of gain and delay time in base-implanted bipolar transistors

This paper uses a numerical analysis, backed by analytic solutions for some cases, to study the dependence of the base component of current gain and delay time in base implanted bipolar transistors on the base impurity porfile. Results are presented in normalised form to facilitate their use in predicting device performance during the processing-device design stage.     

An Indexing Method for Answering Queries on Moving Objects

We consider the problem of indexing a set of objects moving in d-dimensional spaces along linear trajectories. A simple external-memory indexing scheme is proposed to efficiently answer general range queries. The following are examples of the queries that can be answered by the proposed method: report all moving objects that will (i) pass between two given points within a specified time interval; (ii) become within a given distance from some or all of a given set of other moving objects. Our scheme is based on mapping the objects to a dual space, where queries about moving objects are transformed into polyhedral queries concerning their speeds and initial locations. We then present a simple method for answering such polyhedral queries, based on partitioning the space into disjoint regions and using a B+-tree to index the points in each region. By appropriately selecting the boundaries of each region, we guarantee an average search time that matches a known lower bound for the problem. Specifically, for a fixed d, if the coordinates of a given set of N points are statistically independent, the proposed technique answers polyhedral queries, on the average, in O((N/B)^1−1/d⋅(log _B N)^1/d+K/B) I/O's using O(N/B) space, where B is the block size, and K is the number of reported points. Our approach is novel in that, while it provides a theoretical upper bound on the average query time, it avoids the use of complicated data structures, making it an effective candidate for practical applications. The proposed index is also dynamic in the sense that it allows object insertion and deletion in an amortized update cost of log _B(N) I/O's. Experimental results are presented to show the superiority of the proposed index over other methods based on R-trees. recommend Ahmed Elmagarmid     

Scaling merged single-device-well MOSFETs for very large scale integration

Single-Device-Well (SDW) MOSFETs are high density MOSFET structures based on merging two MOSFET devices; a surface channel device and a buried channel device sharing the same device well and the same gate. SDWs offer a potential device area saving of 50%. The merits of the merged SDW MOSFETs are further enhanced in a scaled down MOSFET VLSI technology. This is the subject of this paper.     

A low-power high-performance current-mode multiport SRAM

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-μm CMOS process have shown 2.8 to 9.9× in energy savings and 1.02 to 6.36× reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32×64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach     

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

Low-power design of decimation filters for a digital IF receiver

This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs