Active-pull-down nonthreshold logic BiCMOS circuits for high-speedlow-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 μm BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4× improvement in the load driving capability and 3.4× improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV     

A new model for bipolar transistors at high current

A model for current gain and cutoff frequency falloff at high currents for bipolar transistors is proposed. The model is based on considering that the vertical and lateral base widening occur simultaneously for a typical bipolar transistor. The results of this model successfully fit Pisces-2B simulation results     

Phase-domain fractional-N frequency synthesizers

The concept of phase-domain fractional-N frequency synthesis is presented. Synthesizers using this architecture can achieve fast frequency switching without limiting the minimum channel spacing. In this architecture, a numerical phase comparator is used in conjunction with weighting coefficients, as a linear weighted phase-frequency detector. The synthesizer output spur level is determined by two factors. Namely, the delay of the numerical phase comparator, and the accuracy of the digital-to-analog convertor (DAC) used to convert the phase error to the analog domain. A novel second-order timing-error cancelation scheme is proposed to eliminate the effect of the phase comparator delays. Using this technique together with a 10-bit accuracy DAC, a maximum spur level of less than -65 dBc is simulated for a 900-MHz synthesizer. The settling time of the simulated synthesizer is less than 7 /spl mu/s, and is independent of the channel spacing. The details of the synthesizer architecture, design considerations, and system-level simulations are presented. Implementation issues including the DAC accuracy and timing-error effects are discussed extensively throughout the text.     

Empirical study on multiclass classification‐based network intrusion detection

Early and effective network intrusion detection is deemed to be a critical basis for cybersecurity domain. In the past decade, although a significant amount of work has focused on network intrusion detection, it is still a challenge to establish an intrusion detection system with a high detection rate and a relatively low false alarm rate. In this paper, we have performed a comprehensive empirical study on network intrusion detection as a multiclass classification task, not just to detect a suspicious connection but also to assign the correct type as well. To surpass the previous studies, we have utilized four deep learning models, namely, deep neural networks, long short‐term memory recurrent neural networks, gated recurrent unit recurrent neural networks, and deep belief networks. Our approach relies on the pretraining of the models by exploiting a particle swarm optimization–based algorithm for their hyperparameters selection. In order to investigate the performance differences, we also included two well‐known shallow learning methods, namely, decision forest and decision jungle. Furthermore, we used in our experiments four datasets, which are dedicated to intrusion detection systems to explore various environments. These datasets are KDD CUP 99, NSL‐KDD, CIDDS, and CICIDS2017. Moreover, 22 evaluation metrics are used to assess the model's performance in each of the datasets. Finally, intensive quantitative, Friedman test, and ranking methods analyses of our results are provided at the end of this paper. The results show a significant improvement in the detection of network attacks with our recommended approach.     

An accurate analytical propagation delay model for high-speed CMLbipolar circuits

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i₀ (or load resistor R_L) for a transistor of a certain emitter area when driven by a source of a voltage swing (ΔV) and slew time (t_r ). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits     

Design and optimization of buffer chains and logic circuits in aBiCMOS environment

The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied     

Reliability analysis of photovoltaic systems

Reliability is an important parameter for the user of photovoltaic (PV) power systems. A methodology for the analytical treatment of the reliability of PV systems is proposed in this paper. The method depends upon the logic of the fault-tree technique. The reliabilities of the different components of a PV system are used to predict the reliability of the overall system. Today's most commonly known systems are considered and a reliability formula is developed for each system. The methodology presented is appropriate for a wide range of applications and system types.     

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOSand MTCMOS technologies

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic     

Cobalt-free and samarium-free permanent magnet materials based on an iron-rare earth boride

Ternary iron-praseodymium-boron alloys with 12 at.% Pr and 4 at.% B are potential high-performance permanent magnets in the bulk and respond to conventional processing methods. The magnetic phase is Fe₂₁Pr₃B with a primitive tetragonal lattice ($\text{a}\text{= 0.886}$, c = 1.224 nm). It exhibits high magnetocrystalline anisotropy with a single easy axis along [001]. The systems Fe-La-B and Fe-Nd-B have the same phase with comparable properties.     

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.