Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

Low-power multi-threshold MCML: Analysis, design, and variability

The increasing demand on low-power applications is adding pressure on circuit designers to come out with new circuit styles that can decrease power dissipation while making use of the performance improvement of the new CMOS technologies. Multi-threshold MOS current mode logic (MTMCML) appears to be a solution to this problem by making use of the high-performance of MOS current mode circuits while minimizing power dissipation with the help of multi-threshold CMOS technologies. In this work, analytical formulations, based on the BSIM3v3 model, are proposed for MTMCML performance measures with an error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.     

Analytical and numerical analyses of the delay time of BiCMOSstructures

Analytical expressions for the transient response of BiCMOS structures have been derived. The analysis is performed on conventional structures and structures employing short-channel MOSFETs. The equations relate the delay time to key device and technology parameters. In deriving the time response, the two basic conduction regions (linear and saturation) for the MOSFET have been considered. A numerical algorithm for solving for the delay time of BiCMOS structures taking into account high-level injection effects, base resistance, doping-dependent mobilities, and bandgap narrowing is presented. A figure of merit for the speed is derived and scaling the supply voltage is considered     

Highly testable design of BiCMOS logic circuits

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15%     

High-speed dynamic reference voltage (DRV) CMOS/ECL interfacecircuits

This paper introduces a circuit technique to increase the operating speed of CMOS/ECL interface circuits. The technique is based on shifting the reference voltage dynamically to follow the ECL input signal. HSPICE simulation results based on a 0.8-μm BiCMOS technology show the advantages of DRV CMOS/ECL in terms of speed and noise margins. An analytical delay model which fits HSPICE simulation results is addressed. The error between the model and the circuit simulator is within 4%     

Joint lossless-source and channel coding using ARQ/go-back-(N, M) for image transmission

The paper introduces a new transmission protocol that uses a joint lossless-source and channel coding scheme (JARQ). This protocol utilizes the self-synchronization property of lossless compression to generate indications of errors in the received data. This approach assures the reconstruction of images that were compressed in a lossless fashion and transmitted over a packet switched network, regardless of the error pattern that occurred during transmission. This new protocol is referred to as go-back-(N, M) JARQ. We evaluate the protocol by analyzing its throughput, and present simulation results that compare its throughput with those of conventional ARQ protocols. Using still images, we find significant gain in throughput performance for our go-back-(N, M) protocol, especially in moderate to low BERs, compared with that of the conventional go-back-N protocol. Moreover, by including packet combining, we find large throughput gains at low BERs, as well. This gain is realized for both random and burst errors. This approach provides: an increase in the code rate; a clear indication of error propagation; insensitivity to the type of error pattern - random or burst.     

An economic loss model for failure of sewer pipelines

Estimating the costs of failure for sewer pipelines is usually accompanied with uncertainties because of the difficulty in capturing the relationship between the physical and economical characteristics of failed pipelines. To reduce such uncertainties economic loss models are usually used to evaluate the consequences of failure. This paper presents a methodology to estimate economic loss as a result of sewer pipelines’ failure using cost benefit analysis approach. Costs of sewer pipelines’ failure in addition to costs resulting from avoiding such failures are identified and analysed. To validate the proposed methodology, actual costs from a real failure incident were compared with the proposed model outputs. The model could estimate the direct and indirect costs with a deviation ranging between 10–12% and 22–30%, respectively. By implementing the proposed methodology on two case studies, it was found that the indirect costs as a result of sewer pipelines’ failure represent a significant portion ranging between 89 and 94% of the total costs of failure. Also, it was found that costs related to environment, delays to work and traffic disruptions contribute by 12–35% to the indirect costs.     

Meat quality evaluation by hyperspectral imaging technique: an overview

During the last two decades, a number of methods have been developed to objectively measure meat quality attributes. Hyperspectral imaging technique as one of these methods has been regarded as a smart and promising analytical tool for analyses conducted in research and industries. Recently there has been a renewed interest in using hyperspectral imaging in quality evaluation of different food products. The main inducement for developing the hyperspectral imaging system is to integrate both spectroscopy and imaging techniques in one system to make direct identification of different components and their spatial distribution in the tested product. By combining spatial and spectral details together, hyperspectral imaging has proved to be a promising technology for objective meat quality evaluation. The literature presented in this paper clearly reveals that hyperspectral imaging approaches have a huge potential for gaining rapid information about the chemical structure and related physical properties of all types of meat. In addition to its ability for effectively quantifying and characterizing quality attributes of some important visual features of meat such as color, quality grade, marbling, maturity, and texture, it is able to measure multiple chemical constituents simultaneously without monotonous sample preparation. Although this technology has not yet been sufficiently exploited in meat process and quality assessment, its potential is promising. Developing a quality evaluation system based on hyperspectral imaging technology to assess the meat quality parameters and to ensure its authentication would bring economical benefits to the meat industry by increasing consumer confidence in the quality of the meat products. This paper provides a detailed overview of the recently developed approaches and latest research efforts exerted in hyperspectral imaging technology developed for evaluating the quality of different meat products and the possibility of its widespread deployment.     

Novel merged BiCMOS circuit structures

Novel merged BiCMOS circuit structures are presented. They offer an area saving of 20-30% compared with conventional BiCMOS structures. The DC and the transient performance of the merged structures are verified using the two-dimensional PISCES-IIB device simulator.<>     

Scaling of digital BiCMOS circuits

A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling