A new model for bipolar transistors at high current

A model for current gain and cutoff frequency falloff at high currents for bipolar transistors is proposed. The model is based on considering that the vertical and lateral base widening occur simultaneously for a typical bipolar transistor. The results of this model successfully fit Pisces-2B simulation results     

Phase-domain fractional-N frequency synthesizers

The concept of phase-domain fractional-N frequency synthesis is presented. Synthesizers using this architecture can achieve fast frequency switching without limiting the minimum channel spacing. In this architecture, a numerical phase comparator is used in conjunction with weighting coefficients, as a linear weighted phase-frequency detector. The synthesizer output spur level is determined by two factors. Namely, the delay of the numerical phase comparator, and the accuracy of the digital-to-analog convertor (DAC) used to convert the phase error to the analog domain. A novel second-order timing-error cancelation scheme is proposed to eliminate the effect of the phase comparator delays. Using this technique together with a 10-bit accuracy DAC, a maximum spur level of less than -65 dBc is simulated for a 900-MHz synthesizer. The settling time of the simulated synthesizer is less than 7 /spl mu/s, and is independent of the channel spacing. The details of the synthesizer architecture, design considerations, and system-level simulations are presented. Implementation issues including the DAC accuracy and timing-error effects are discussed extensively throughout the text.     

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

Reliability analysis of photovoltaic systems

Reliability is an important parameter for the user of photovoltaic (PV) power systems. A methodology for the analytical treatment of the reliability of PV systems is proposed in this paper. The method depends upon the logic of the fault-tree technique. The reliabilities of the different components of a PV system are used to predict the reliability of the overall system. Today's most commonly known systems are considered and a reliability formula is developed for each system. The methodology presented is appropriate for a wide range of applications and system types.     

Cobalt-free and samarium-free permanent magnet materials based on an iron-rare earth boride

Ternary iron-praseodymium-boron alloys with 12 at.% Pr and 4 at.% B are potential high-performance permanent magnets in the bulk and respond to conventional processing methods. The magnetic phase is Fe₂₁Pr₃B with a primitive tetragonal lattice ($\text{a}\text{= 0.886}$, c = 1.224 nm). It exhibits high magnetocrystalline anisotropy with a single easy axis along [001]. The systems Fe-La-B and Fe-Nd-B have the same phase with comparable properties.     

Joint lossless-source and channel coding using ARQ/go-back-(N, M) for image transmission

The paper introduces a new transmission protocol that uses a joint lossless-source and channel coding scheme (JARQ). This protocol utilizes the self-synchronization property of lossless compression to generate indications of errors in the received data. This approach assures the reconstruction of images that were compressed in a lossless fashion and transmitted over a packet switched network, regardless of the error pattern that occurred during transmission. This new protocol is referred to as go-back-(N, M) JARQ. We evaluate the protocol by analyzing its throughput, and present simulation results that compare its throughput with those of conventional ARQ protocols. Using still images, we find significant gain in throughput performance for our go-back-(N, M) protocol, especially in moderate to low BERs, compared with that of the conventional go-back-N protocol. Moreover, by including packet combining, we find large throughput gains at low BERs, as well. This gain is realized for both random and burst errors. This approach provides: an increase in the code rate; a clear indication of error propagation; insensitivity to the type of error pattern - random or burst.     

Low-power BiCMOS circuits for high-speed interchip communication

A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Using a 3.3 V supply, the novel transceiver can drive/receive signals from several low-voltage-swing transceivers with termination voltages ranging from 5 V down to 2 V and frequencies well above 1 GHz. Measured results of test circuits fabricated in 0.8-μm BiCMOS technology are also presented