A simple simultaneous geometric and intensity correction method for echo-planar imaging by EPI-based phase modulation

A technique, based on Echo planar imaging (EPI)-based phase modulation factor maps, is described for correction of EPI distortions resulting from field inhomogeneity. In this paper, a phase modulation factor was employed to remove the distortions. The phase modulation factor was obtained experimentally by collecting EPI images with a spin-echo (TE) spacing, deltaTE, equal to the inter-echo time interval, T(i). Then, the distortions resulting from the field inhomogeneity were removed by modulating the kappa-space data with the phase modulation factor. One of the advantages of this method is that it requires only a few extra scans to collect the information on field inhomogeneity. The proposed method does not require a phase unwrapping procedure for field inhomogeneity correction and, hence, is easier to implement, compared to other techniques. In addition, it corrects geometric distortion as well as intensity distortions simultaneously, which is robust to external noise or estimation error in severely distorted images. In this work, we also compared the proposed technique with others including, a) interpolation method with EPI-based displacement maps, and b) modulation method with phase modulation factor maps generated from spin-echo images. The results suggest the proposed technique is superior in correcting severely distorted images.     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.     

Efficient electron beam condensing for low-energy microcolumn lithography

Low-energy electron beam lithography has been performed with a microcolumn by adopting a new technique that condenses the electron beam efficiently. To increase the probe current while keeping the kinetic energy of electrons sufficiently low, the negative or positive bias has been applied to the accelerator electrode, which reduces the divergence of the electron beam and hence makes more electrons pass through the microcolumn. With this technique, the probe current more than 1 nA has been achieved, which is large enough for the practical application of microcolumn lithography even when the kinetic energy of electrons is as low as 160 eV. The results of microcolumn lithography by using the condensed electron beam with a low-energy of 160 and 327 eV are also presented.     

Ultra-High Capacity and Cyclability of β-phase Ca0.14V2O5 as a Promising Cathode in Calcium-Ion Batteries

Crystalline water-free β-phase Ca_0.14V₂O₅ is reported for the first time as a viable cathode material for calcium-ion batteries (CIBs). In contrast to layered α-V₂O₅ and δ-Ca_xV₂O₅·nH₂O, which have limited capacity, the β-phase delivers a reversible capacity of ≈247 mAh g⁻¹, which corresponds to the insertion/extraction of Ca²⁺ between Ca_0.14V₂O₅ and Ca_1.0V₂O₅. The process of Ca²⁺ insertion process and the accompanying structural relaxation are theoretically and experimentally verified. The initial insertion of Ca²⁺ into Ca_0.14V₂O₅ causes a slight shift of oxygen atoms surrounding hepta-coordination sites, creating penta-coordinated sites that are then partially filled up to Ca_0.33V₂O₅. Further insertion occurs through the stepwise occupation of up to 50% of neighboring hexa- and tetra-coordination sites to form Ca_0.67V₂O₅ and Ca_1.0V₂O₅, respectively. The rearrangement of oxygen atoms in Ca_0.14V₂O₅ also minimizes dimensional changes, leading to high cyclic stability during repeated charge/discharge cycles. The remarkable electrochemical performance of full cells containing a Ca_0.14V₂O₅ cathode and a K metal anode in Ca²⁺/K⁺ hybrid electrolytes, is also demonstrated, thanks to the inertness of K⁺ insertion into Ca_0.14V₂O₅ and the absence of calcium plating/stripping. The cyclic stability and high capacity of Ca_0.14V₂O₅ is not compromised in hybrid electrolytes, making it a viable CIB cathode.     

High-speed CMOS demultiplexer with redundant multi-valued logic

This paper describes an 11-Gb/s CMOS demultiplexer with redundant multi-valued logic. The proposed circuit receives serial binary data which is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the redundant multi-valued logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. The circuit is designed with a 0.35?µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The demultiplexer is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43?mW. This circuit is expected to operate at a higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.     

Asymptotic analysis of mutual coupling in concave circularcylindrical arrays. II. Near-zone

For pt.I, see ibid., vol.41, no.2, p.121-36 (1993). This work evaluates the near-zone coupling coefficients in large concave arrays. A canonical model of a circular cylindrical concave array of open-ended rectangular waveguides is analyzed. It is shown that in the paraxial region (which also includes the area close to the excited element) the coupling coefficients are identical, to lowest asymptotic order, to those in an equivalent infinite planar array. In the transition region, which lies between the paraxial and the far zone, or the ray region, two representations were developed: one, a transition function, expressed in terms of a canonical integral which must be numerically evaluated, and the other a uniform representation, which consists of a superposition of a planar array contribution and a few periodic structure rays. The uniform representation is valid in the near zone (which includes both the paraxial and the transition region) as well as in the far zone. This form is simple and may be immediately generalized to concave arrays with slowly varying curvature and periodicity     

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period     

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byteeffective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm² and an effective cell size of 1.1 μm²     

Algorithm for mapping between information bits and channel symbolsin MTCM codes

An algorithm for mapping between information bits and channel symbols in multiple trellis-coded modulation (MTCM) codes with M-PSK signal sets is proposed. The core of the algorithm assigns information bits with a Hamming distance in proportion to the sum of the Euclidean distance to each M-PSK symbol. The analytical results show that the additional gains from applying the algorithm can be achieved with little or no loss     

Development of the Base Station Controller and Manager in the CDMA Mobile System

The base station (BS) in the CDMA Mobile System (CMS) connects calls through the radio interface and is designed to provide mobile subscribers with high quality service in spite of mobile subscribers’ motions. The BS consists of multiple base station transceiver subsystems (BTSs), a base station controller (BSC) and a base station manager (BSM). This paper is concerned with the BSC and the BSM. The BSC is located between the BTSs and the mobile switching center (MSC) connected with the public network, and is responsible for controlling mobile calls from and to mobile subscribers via the BTSs. The BSM provides operator-interfaces per the BS and takes responsibility of operation and maintenance (OAM) of the BS. Design of the BSC is based on two module types: functional module and unit module. The functional module is used to support new services easily and the unit module to increase the system capacity economically. Both modular types are easily achieved by inserting the corresponding modules to the system. Particularly, in order to efficiently support the soft handover which is one of CDMA superior advantages, the BSC adopts a large high-speed packet switch connecting up to 512 BTSs, and thus mobile subscribers can be provided with soft handover in high probability. The BSM is based on a commercial workstation to support OAM functions efficiently and guarantee high reliability of the functions. The BSM uses graphical user interface (GUI) for efficient OAM functions of the BS.