A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

Multicast-based inference of network-internal delay distributions

Packet delay greatly influences the overall performance of network applications. It is therefore important to identify causes and locations of delay performance degradation within a network. Existing techniques, largely based on end-to-end delay measurements of unicast traffic, are well suited to monitor and characterize the behavior of particular end-to-end paths. Within these approaches, however, it is not clear how to apportion the variable component of end-to-end delay as queueing delay at each link along a path. Moreover, there are issues of scalability for large networks. In this paper, we show how end-to-end measurements of multicast traffic can be used to infer the packet delay distribution and utilization on each link of a logical multicast tree. The idea, recently introduced in Caceres et al. (1999), is to exploit the inherent correlation between multicast observations to infer performance of paths between branch points in a tree spanning a multicast source and its receivers. The method does not depend on cooperation from intervening network elements; because of the bandwidth efficiency of multicast traffic, it is suitable for large-scale measurements of both end-to-end and internal network dynamics. We establish desirable statistical properties of the estimator, namely consistency and asymptotic normality. We evaluate the estimator through simulation and observe that it is robust with respect to moderate violations of the underlying model.     

The future of wires

Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-μm to 0.035-μm feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these “local” wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms     

Low‐Operating‐Voltage Organic Transistors Made of Bifunctional Self‐Assembled Monolayers

Self‐assembled monolayers (SAMs) are molecular assemblies that spontaneously form on an appropriate substrate dipped into a solution of an active surfactant in an organic solvent. Organic field‐effect transistors are described, built on an SAM made of bifunctional molecules comprising a short alkyl chain linked to an oligothiophene moiety that acts as the active semiconductor. The SAM is deposited on a thin oxide layer (alumina or silica) that serves as a gate insulator. Platinum–titanium source and drain electrodes (either top‐ or bottom‐contact configuration) are patterned by using electron‐beam (e‐beam) lithography, with a channel length ranging between 20 and 1000 nm. In most cases, ill‐defined current–voltage (I–V) curves are recorded, attributed to a poor electrical contact between platinum and the oligothiophene moiety. However, a few devices offer well‐defined curves with a clear saturation, thus allowing an estimation of the mobility: 0.0035 cm² V^–1 s^–1 for quaterthiophene and 8 × 10^–4 cm² V^–1 s^–1 for terthiophene. In the first case, the on–off ratio reaches 1800 at a gate voltage of –2 V. Interestingly, the device operates at room temperature and very low bias, which may open the way to applications where low consumption is required.     

Passivity based visual servoing of mobile robots with dynamics compensation

This paper presents an image-based dynamic visual servoing to make a mobile robot able to track a moving object on the workspace by using a calibrated on board vision system. The stability of the proposed system is proved based on its passivity properties. A robustness analysis and an L₂-gain performance analysis are also presented. Experimental results are shown to illustrate the system performance.     

The implementation of a 2-core, multi-threaded itanium family processor

The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation. The most obvious being the incorporation of two legacy cores on-die and at the same time reducing power by 23%. This is an effective 325% increase in MIPS per watt which necessitated a holistic focus on power reduction and management. The next challenge in the implementation was to ensure robust and high frequency circuit operation in the 90-nm process generation which brings with it higher leakage and greater variability. Achieving this goal required new methodologies for design, a greatly improved and tunable clock system and a better understanding of our power grid behavior all of which required new circuits and capabilities. The final aspect of circuit design improvement involved the I/O design for our legacy multi-drop system bus. To properly feed the two high frequency cores with memory bandwidth we needed to ensure frequency headroom in the operation of the bus. This was achieved through several innovations in controllability and tuning of the I/O buffers which are discussed as well.     

Identification of elastic, dielectric, and piezoelectric constants in piezoceramic disks

Three-dimensional modeling of piezoelectric devices requires a precise knowledge of piezoelectric material parameters. The commonly used piezoelectric materials belong to the 6mm symmetry class, which have ten independent constants. In this work, a methodology to obtain precise material constants over a wide frequency band through finite element analysis of a piezoceramic disk is presented. Given an experimental electrical impedance curve and a first estimate for the piezoelectric material properties, the objective is to find the material properties that minimize the difference between the electrical impedance calculated by the finite element method and that obtained experimentally by an electrical impedance analyzer. The methodology consists of four basic steps: experimental measurement, identification of vibration modes and their sensitivity to material constants, a preliminary identification algorithm, and final refinement of the material constants using an optimization algorithm. The application of the methodology is exemplified using a hard lead zirconate titanate piezoceramic. The same methodology is applied to a soft piezoceramic. The errors in the identification of each parameter are statistically estimated in both cases, and are less than 0.6% for elastic constants, and less than 6.3% for dielectric and piezoelectric constants.     

Methods for true energy-performance optimization

This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivity-based optimizations minimize energy subject to a delay constraint. Energy savings of about 65% can be achieved without delay penalty with equalization of sensitivities to sizing, supply, and threshold voltage in a 64-bit adder, compared to the reference design sized for minimum delay. Circuit optimization is effective only in the region of about /spl plusmn/30% around the reference delay; outside of this region the optimization becomes too costly either in terms of energy or delay. Using optimal energy-delay tradeoffs from the circuit level and introducing more degrees of freedom, the optimization is hierarchically extended to higher abstraction layers. We focus on the micro-architectural optimization and demonstrate that the scope of energy-efficient optimization can be extended by the choice of circuit topology or the level of parallelism. In a 64-bit ALU example, parallelism of five provides a three-fold performance increase, while requiring the same energy as the reference design. Parallel or time-multiplexed solutions significantly affect the area of their respective designs, so the overall design cost is minimized when optimal energy-area tradeoff is achieved.     

Composite with Recyclable Loads for the Manufacture of Blocks to Build Popular Houses

The science space in a state school in Natal city was built using a composite consisting of gypsum, EPS （expanded polystyrene）, shredded tire, cement and water. Mechanical and thermal resistances were evaluated. Inside the blocks, three types of fillings （EPS plates, aluminum cans and 500 mL bottles of mineral water） were placed in order to obtain a walls with higher thermal resistance, but also to give it an ecologically correct order, considering that both the tire and the EPS occupy a large space in landfills and require years to be degraded when released into the environment. Compression tests were conducted according to the rules. The experiments demonstrated that the temperature difference between the internal and external surfaces on the walls reached levels above 12.0 ℃. It was also demonstrated that the proposed composite has adequate mechanical strength to be used for sealing walls. The proposed use of the composite can contribute to reduce the significant housing deficit of Brazil, producing popular houses at low cost and with little time to work.