The partial substitution of Ga at the Cu(1) (chain) sites of the YBa2Cu3O7 structure allows synthesis at ambient pressure of Ba-free analogs, e.g., YSr2Cu2.7Ga0.3O7–
. Materials with this composition have been found to be nonsuperconducting, but superconductivity has been induced by one or more of the following methods: Ca substitutions at the Y site; Ba substitutions at the Sr site; annealing in high-pressure oxygen. The influence of these chemical manipulations onTc has been monitored and all methods have been found to enhanceTc. The electronic effects of Ba substitutions have been deduced indirectly using powder neutron diffraction, and such substitutions appear to result in a redistribution of hole density into the Cu(1) sites from the superconducting CuO2 planes. 相似文献
The superconducting properties of Y1–yCaySr2Cu2GaO7– have been examined and related to the Ca content,y, and the use of annealing treatments at 350 bar oxygen. Superconductivity withTc up to 41 K was found only for high-pressure-annealed samples, and the structural effects of Ca substitution and high-pressure treatment were examined using powder neutron diffraction. Small but significant changes in Cu-Cu and Cu-O distances were found and suggest that the Cu ions are more highly charged in superconducting samples. Partial substitution of Ba for Sr was found to be possible (up to 20%) to give samples which, after annealing in high-pressure oxygen, were superconducting at temperatures up to 68 K. 相似文献
The Low-Density Parity Check (LDPC) codes of Euclidean Geometry (EG) are encrypted and decrypted in numerous ways, namely Soft Bit Flipping (SBF), Sequential Peeling Decoder (SPD), Belief Propagation Decoder (BPD), Majority Logic Decoder/Detector (MLDD), and Parallel Peeling Decoder (PPD) decoding algorithms. These algorithms provide aextensive range of trade-offs between latency decoding, power consumption, hardware complexity-required resources, and error rate performance. Therefore, the problem is to communicate a sophisticated technique specifying the both soft and burst errors for effective information transmission. In this research, projected a technique named as Hybrid SBF (HSBF) decoder for EG-LDPC codes, which reduces the decoding complexity and maximizes the signal transmission and reception. In this paper, HSBF is also known as Self Reliability based Weighted Soft Bit Flipping (SRWSBF) Decoder. It is obvious from the outcomes that the proposed technique is better than the decoding algorithms SBF, MLDD, BPD, SPD and PPD. Using Xilinx synthesis and SPARTAN 3e, a simulation model is designed to investigate latency, hardware utilization and power consumption. Average latency of 16.65 percent is found to be reduced. It is observed that in considered synthesis parameters such as number of 4-input LUTs, number of slices, and number of bonded IOBs, excluding number of slice Flip-Flops, hardware utilization is minimized to an average of 4.25 percent. The number of slices Flip-Flops resource use in the proposed HSBF decoding algorithm is slightly higher than other decoding algorithms, i.e. 1.85%. It is noted that, over the decoding algorithms considered in this study, the proposed research study minimizes power consumption by an average of 41.68%. These algorithms are used in multimedia applications, processing systems for security and information.
Fault detection and classification is a key challenge for the protection of High Voltage DC (HVDC) transmission lines.
In this paper, the Teager–Kaiser Energy Operator (TKEO) algorithm associated with a decision tree-based fault classi
f
ier is proposed to detect and classify various DC faults. The Change Identification Filter is applied to the average and
differential current components, to detect the first instant of fault occurrence (above threshold) and register a Change
Identified Point (CIP). Further, if a CIP is registered for a positive or negative line, only three samples of currents (i.e.,
CIP and each side of CIP) are sent to the proposed TKEO algorithm, which produces their respective 8 indices through
which the, fault can be detected along with its classification. The new approach enables quicker detection allowing
utility grids to be restored as soon as possible. This novel approach also reduces computing complexity and the time
required to identify faults with classification. The importance and accuracy of the proposed scheme are also thor
oughly tested and compared with other methods for various faults on HVDC transmission lines. 相似文献
In this paper, an all-optical miniaturized binary to gray code converter is designed and analyzed. The all-optical domain is now an alternative for electronic devices, where performance and speed are the key issues. Code converters are significantly used in digital data transmission in the areas of error detection and correction. Gray code is one of the cyclic codes, where the cyclic shift of each codeword is also a code word. An all-optical XOR gate, realized using a Y-shaped power combiner is used in this design to generate the desired gray code from the given binary code. The insertion loss and extinction ratio parameters are found to be 0.347 dB and 22.26 dB, respectively. The entire simulation is carried out using finite-difference time-domain method. The obtained practical results are verified mathematically using MATLAB.
The concept of cloud envisioned cyber-physical systems is a practical technology that allows users to interact with each other while transferring data in the cloud. In cyber-physical systems, cloud storage utilizes data deduplication techniques to improve the performance of its applications. However, this method exposes sensitive data and causes security risks. Various research related to cloud storage has been conducted. Despite the advantages of this technology, it lacks the necessary security features and high performance. In the proposed method, a victim's virtual computer is moved to the cloud without interfering with the other processes running on the network. It protects against the attacks caused by encrypting the data with a cryptographically binding hash. Post-Quantum Cryptographic techniques, such as lightweight Multi-Extractable Somewhere Statistically Binding and Learning With Error authenticate data sharing protocols (MESSB–LWE), have been used. These allow for safe data sharing across geographically scattered physical devices and clients with lightweight concepts. The numerical analysis of MESSB–LWE is carried out in different stages, and the results show that it has incredible performance and practicality when compared to the literature. Finally, the authors have explored a couple of factors that should be considered for future research work in authentication for securing remote systems in the cloud environment.
Microsystem Technologies - In this paper synthesis of two wideband Metamaterial Cross Polarizer (MCPs) is proposed. The synthesis of proposed MCPs is done by using Binary Wind Driven Optimization... 相似文献
Developing light weight polymer based composites dispersed with novel reinforcements which can function well in the presence of aggressive environments is an active research field in the materials engineering. Hence, in the current work, halloysite nanotubes (1 %, 2 %, 4 %, 6 %, 8 % and 10 % by weight) were reinforced into acrylonitrile butadiene styrene/polycarbonate blend and the role of reinforcing phases on the mechanical performance under aggressive environmental conditions has been evaluated. Hardness was measured as gradually increased in the composites with the increased content of the reinforcements. Impact strength of the composites was observed as increased in the composites up to 4 % reinforcement and further decreased. Increased strength was measured for the composite up to 2 % reinforcement. Ductility of the composites was decreased as reflected form the decreased % of elongation with the higher fraction of reinforcements due to induced brittleness. The composites were exposed to diluted sulfuric acid for 3 h and 6 h at 60 °C and then subjected to tensile loading. With the increased time of exposure, composites with 1 % and 2 % reinforcement exhibited relatively better performance. 相似文献
Failure diagnosability has been widely studied for discrete event system (DES) models because of modeling simplicity and computational
efficiency due to abstraction. In the literature it is often held that for diagnosability, such models can be used not only
for systems that fall naturally in the class of DES but also for the ones traditionally treated as continuous variable dynamic
systems. A class of algorithms for failure diagnosability of DES models has been successfully developed for systems where
fairness is not a part of the model. These algorithms are based on detecting cycles in the normal and the failure model that
look identical. However, there exist systems with all transitions fair where the diagnosability condition that hinges upon
this feature renders many failures non-diagnosable although they may actually be diagnosable by transitions out of a cycle.
Hence, the diagnosability conditions based on cycle detection need to be modified to hold for many real-world systems where
all transitions are fair. In this work, however, it is shown by means of an example that a system may have some transitions
fair and some unfair. A new failure diagnosability mechanism is proposed for DES models with both fair and unfair transitions.
Time complexity for deciding diagnosability of DES models with fair and unfair transitions is analyzed and compared with the
time complexities of other DES diagnosability analysis methods reported in the literature. 相似文献
All elliptic curve cryptographic schemes are based on scalar multiplication of points, and hence its faster computation signifies faster operation. This paper proposes two different parallelization techniques to speedup the GF(p) elliptic curve multiplication in affine coordinates and the corresponding architectures. The proposed implementations are capable of resisting different side channel attacks based on time and power analysis. The 160, 192, 224 and 256 bits implementations of both the architectures have been synthesized and simulated for both FPGA and 0.13μ CMOS ASIC. The final designs have been prototyped on a Xilinx Virtex-4 xc4vlx200-12ff1513 FPGA board and performance analyzes carried out. The experimental result and performance comparison show better throughput of the proposed implementations as compared to existing reported architectures. 相似文献