采用全对称测试结构的超薄单晶硅薄膜热导率测亮

改进了传统稳态加热法的测试结构,设计了带隔离槽的全对称悬空薄膜测试结构,并使用有限元工具对测试结构进行了优化.测量了室温下50和80nm厚度的单晶硅薄膜的横向热导率,分别为32和38W/(m·K),其相对体硅热导率(148W/(m·K))有明显下降,实验结果与BTE(Boltzmann transport equation)的理论预测曲线吻合得很好.     

数值分析渐变DBR对垂直腔面发射激光器谐振腔模的影响

通过数值分析研究了含线性渐变层的Al0.9Ga0.1As/AlyGa1-yAs/GaAs/AlxGa1-xAS DBR的光学特性及其对VCSEL谐振腔光学特性的影响,建立了渐变型DBR渐变层厚度与折射率的关系,通过特征矩阵法计算了突变GaAs/Al0.9Ga0.1AS DBR和渐变型DBR的反射谱和反射相移,分析了渐变层对DBR反射率和反射相移的影响.对渐变型DBR,要使VCSEL谐振腔满足中心波长相位匹配条件,还需要在DBR靠近谐振腔一侧的最前面增加一定厚度的渐变层,称为相位匹配层.通过计算,我们得到了使VCSEL谐振腔满足相位匹配条件时均匀层和相位匹配层的厚度.     

一种新颖的应变Si沟道 pMOSFET制作技术

在应变Si沟道异质结场效应晶体管(HFET)制作过程中,引入分子束外延(MBE)低温Si(LT-Si)技术,大大减少了弛豫SiGe层所需的厚度.TEM结果表明,应变Si层线位错密度低于106cm-2.原子力显微镜(AFM)测试表明,其表面均方粗糙度小于1.02nm.器件测试结果表明,与相同条件下的体Si pMOSFET相比,空穴迁移率提高了25%.     

集成CMOS四象限模拟乘法器

给出了一种CMOS型四象限模拟乘法器,该乘法器采用有源衰减器结合吉尔伯特单元结构.利用基于CSMC的0.6μm n阱2p2m工艺SPICE BSIM3V3 MOS模型(level=49)进行仿真,采用单电源5V电压供电.利用HSPICE仿真并给出了仿真的结果及版图实现.     

高速12位D/A转换器

介绍了高速12位D/A转换器的电路设计,采用2μm等平面高速双极工艺,研制出数据更新率≥80MHz,线性误差≤3LSB,微分非线性≤3LSB的12位D/A转换器电路.     

Design of Ultra-Wideband Monopulse Receiver

In this paper, we propose a novel amplitude-comparison monopulse receiver architecture for ultra-wideband radars. This monopulse receiver consists of four ridged-horn antennas placed in a square-feed configuration, a comparator circuit that generates the monopulse sum and difference signals, cross-correlation receivers that detect the monopulse signals, and an amplitude-comparison monopulse processor that determines the target's angular position. The derived monopulse sum and difference signals are verified through measurements. The derived sum and difference patterns are compared with measured patterns, and they show good agreements-measured 3-dB beamwidth=6.4deg(derived=6deg), measured unambiguous tracking range=plusmn5deg(derived=plusmn5deg), and measured sum pattern sidelobe level=-6 dB (derived=-8 dB)     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

基于类渗流导电的超薄栅氧化层软击穿后的电流模拟

研究了超薄栅氧化层(≤3.0nm)软击穿(soft breakdown,SBD)后的栅电流和衬底电流特性.提出了一个基于类渗流导电的SBD后栅电流和衬底电流的解析公式--类渗流导电公式.该公式能够在较大的电压范围(-4～+3V)模拟氧化层SBD后的栅电流和衬底电流的电流-电压特性,为超薄栅氧化层可靠性的研究提供了一个较为简便的公式.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

低阻p型衬底上高阻厚层n型外延

介绍了高阻厚层反型外延片的一种实用生产技术，即在PE-2061S外延设备上，采取特殊的工艺控制在电阻率小于0.02Ω·cm的p型低阻衬底上实现了高阻厚层n型外延生长，外延层电阻率大于40Ω·cm，厚度大于100μm. 研究表明：该外延材料完全可以满足IGBT器件制作的需要.