An Analysis of Consumer Preferences among Wireless LAN and Mobile Internet Services

Wireless data communication (WDC) services are increasingly penetrating the market. The two main alternative WDC technologies are wireless LAN and mobile Internet. Services based on these technologies display differences in quality attributes such as terminal device, data transmission speed, pricing scheme and so on. How consumers choose between these two alternatives will be determined by their preferences regarding such quality attributes. In turn, their preferences will affect the evolution of WDC services and related technologies. This study employs a conjoint analysis of consumer valuations of quality attributes of wireless LAN and mobile Internet services. Respondents rate hypothetical service alternatives featuring various combinations of quality attributes. By estimating consumer willingness to pay for the attributes of WDC services, the authors predict the evolution of WDC services and related technologies along various quality dimensions, make a comparison with the results of a previous study, and draw policy implications for national‐and company‐level R&D strategies.     

Data Clustering Method Using a Modified Gaussian Kernel Metric and Kernel PCA

Most hyper‐ellipsoidal clustering (HEC) approaches use the Mahalanobis distance as a distance metric. It has been proven that HEC, under this condition, cannot be realized since the cost function of partitional clustering is a constant. We demonstrate that HEC with a modified Gaussian kernel metric can be interpreted as a problem of finding condensed ellipsoidal clusters (with respect to the volumes and densities of the clusters) and propose a practical HEC algorithm that is able to efficiently handle clusters that are ellipsoidal in shape and that are of different size and density. We then try to refine the HEC algorithm by utilizing ellipsoids defined on the kernel feature space to deal with more complex‐shaped clusters. The proposed methods lead to a significant improvement in the clustering results over K‐means algorithm, fuzzy C‐means algorithm, GMM‐EM algorithm, and HEC algorithm based on minimum‐volume ellipsoids using Mahalanobis distance.     

Reconstructed Water Oxidation Electrocatalysts: The Impact of Surface Dynamics on Intrinsic Activities

Electroreduction of small molecules such as H₂O, CO₂, and N₂ for producing clean fuels or valuable chemicals provides a sustainable approach to meet the increasing global energy demands and to alleviate the concern on climate change resulting from fossil fuel consumption. On the path to implement this purpose, however, several scientific hurdles remain, one of which is the low energy efficiency due to the sluggish kinetics of the paired oxygen evolution reaction (OER). In response, it is highly desirable to synthesize high-performance and cost-effective OER electrocatalysts. Recent advances have witnessed surface reconstruction engineering as a salient tool to significantly improve the catalytic performance of OER electrocatalysts. In this review, recent progress on the reconstructed OER electrocatalysts and future opportunities are discussed. A brief introduction of the fundamentals of OER and the experimental approaches for generating and characterizing the reconstructed active sites in OER nanocatalysts are given first, followed by an expanded discussion of recent advances on the reconstructed OER electrocatalysts with improved activities, with a particular emphasis on understanding the correlation between surface dynamics and activities. Finally, a prospect for clean future energy communities harnessing surface reconstruction-promoted electrochemical water oxidation will be provided.     

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

A low-power, area-efficient four-way 32-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single-cycle throughput and the small-size low-power unification of various complicated arithmetic operations such as power, logarithm, trigonometric functions, vector-SIMD multiplication, division, square root and vector dot product. 24-region and 16-region piecewise linear logarithmic and antilogarithmic converters are proposed with 0.8% and 0.02% maximum conversion error, respectively. All the supported operations are implemented with less than 6.3% operation error and unified into a single arithmetic platform with maximum four-cycle latency and single-cycle throughput. A 93 K gate test chip is fabricated using one-poly five-metal 0.18-mum CMOS technology. It operates at 210 MHz with maximum power consumption of 15.3 mW at 1.8 V.     

A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

This paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and highspeed human body communication (HBC) utilizes a digital transceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50-Omega impedance. The channel investigation with the DCI identities an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a direct digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscillator and a quadratic sampling technique. The WBS digital transceiver chip with a 0.25-mum standard CMOS technology has 2-Mb/s data rate at a bit error rate of 1.1 times 10^-7, dissipating only 0.2 mW from a 1-V supply generated by a 1.5-V battery.     

An experimental study on time delay control of actuation system of tilt rotor unmanned aerial vehicle

This paper presents an actuation control system for the Smart Unmanned Aerial Vehicle (SUAV), a tilt rotor aircraft that is being developed by the Korea Aerospace Research Institute. The actuation system, which consists of flaperon, rotor, and nacelle tilt, should be controlled to track the position command sent from the flight controller. However, substantial variations in the aerodynamic load on the actuation system make it difficult to achieve the desired level of control performance. In this study, the actuation system was controlled using the Time Delay Control (TDC) law. The experimental results show that the following control performance specifications are completely satisfied under load variation from 0 to 455 kgf: bandwidth of 4 Hz, overshoot of 2.5%, and steady state error of 1% for flaperon and rotor actuation system. Especially, the accuracy was within the noise level of the steady state position error over broad ranges of the load. In addition, the command filter was applied to the TDC command to mitigate the effects of the phase delay that occurs when a sinusoidal command is applied. Furthermore, an actual flight test was performed, which clearly showed the effectiveness of the proposed control scheme. This promising control performance shows that TDC is an effective alternative for controlling the actuation system of the SUAV with substantial load variation.     

Jitter and Amplitude Noise Accumulations in Cascaded All-Optical Regenerators

This paper proposes and demonstrates a simulation model to systematically investigate jitter accumulations in cascaded all-optical 2R regenerators. The simulation results indicate that when the pattern dependence from the memory effect is minimized, the jitter accumulation depends critically on the degree of the regenerative nonlinearity. Studies of tradeoffs between the jitter from bandwidth limitation and the signal-to-noise-ratio degradation help identify the optimized regenerator bandwidth for various degrees of regenerative nonlinearity. The simulation then considers the pattern dependence from the memory effect and finds that it can severely degrade the cascadability of an optical 2R regenerator and can make it worse than that of a linear optical amplifier (optical 1R). The simulation results show good matches to the experimental results of an optical 2R regenerator based on a semiconductor optical amplifier based Mach-Zehnder interferometer. To overcome the jitter accumulation associated with the optical 2R regeneration, we experimentally demonstrate an optical 3R regenerator for optical nonreturn-to-zero signals with all-optical clock recovery. The experiments achieve more than 1000-hop cascadability for pseudorandom binary sequence 2³¹-1 inputs with a 100-km recirculation loop using lab fiber. Field trial experiments then demonstrate a more than 1000-hop cascadability for a 3R spacing of 66 km and a 100-hop cascadability for a 3R spacing of 264 km.     

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip

In multiprocessor system-on-chip, tasks and communications should be scheduled carefully since their execution order affects the performance of the entire system. When we implement an MPSoC according to the scheduling result, we may find that the scheduling result is not correct or timing constraints are not met unless it takes into account the delays of MPSoC architecture. The unexpected scheduling results are mainly caused from inaccurate communication delays and or runtime scheduler’s overhead. Due to the big complexity of scheduling problem, most previous work neglects the inter-processor communication, or just assumes a fixed delay proportional to the communication volume, without taking into consideration subtle effects like the communication congestion and synchronization delay, which may change dynamically throughout tasks execution. In this paper, we propose an accurate scheduling model of hardware/software communication architecture to improve timing accuracy by taking into account the effects of dynamic software synchronization and detailed hardware resource constraints such as communication congestion and buffer sharing. We also propose a method for runtime scheduler implementation and consider its performance overhead in scheduling. In particular, we introduce efficient hardware and software scheduler architectures. Furthermore, we address the issue of centralized implementation versus distributed implementation of the schedulers. We investigate the pros and cons of the two different scheduler implementations. Through experiments with significant demonstration examples, we show the effectiveness of the proposed approach.     

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease     

A 0.25-μm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-mum CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 mus channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides -105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm² and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply