High-Performance Al–Sn–Zn–In–O Thin-Film Transistors: Impact of Passivation Layer on Device Stability

We fabricated high-performance thin-film transistors (TFTs) with an amorphous-Al–Sn–Zn–In–O (a-AT-ZIO) channel deposited by cosputtering using a dual Al–Zn–O and In–Sn–O target. The fabricated AT-ZIO TFTs, which feature a bottom-gate and bottom-contact configuration, exhibited a high field-effect mobility of 31.9 $ hbox{cm}^{2}/hbox{V}cdothbox{s}$, an excellent subthreshold gate swing of 0.07 V/decade, and a high $I_{{rm on}/{rm off}}$ ratio of $≫hbox{10}^{9}$, even below the process temperature of 250 $^{circ}hbox{C}$. In addition, we demonstrated that the temperature and bias-induced stability of the bottom-gate TFT structure can significantly be improved by adopting a suitable passivation layer of atomic-layer-deposition-derived $hbox{Al}_{2} hbox{O}_{3}$ thin film.      

Fabrication of Sub‐10 nm Metallic Lines of Low Line‐Width Roughness by Hydrogen Reduction of Patterned Metal–Organic Materials

The fabrication of very narrow metal lines by the lift‐off technique, especially below sub‐10 nm, is challenging due to thinner resist requirements in order to achieve the lithographic resolution. At such small length scales, when the grain size becomes comparable with the line‐width, the built‐in stress in the metal film can cause a break to occur at a grain boundary. Moreover, the line‐width roughness (LWR) from the patterned resist can result in deposited metal lines with a very high LWR, leading to an adverse change in device characteristics. Here a new approach that is not based on the lift‐off technique but rather on low temperature hydrogen reduction of electron‐beam patterned metal naphthenates is demonstrated. This not only enables the fabrication of sub‐10 nm metal lines of good integrity, but also of low LWR, below the limit of 3.2 nm discussed in the International Technology Roadmap for Semiconductors. Using this method, sub‐10 nm nickel wires are obtained by reducing patterned nickel naphthenate lines in a hydrogen‐rich atmosphere at 500 °C for 1 h. The LWR (i.e., 3 σ_LWR) of these nickel nanolines was found to be 2.9 nm. The technique is general and is likely to be suitable for fabrication of nanostructures of most commonly used metals (and their alloys), such as iron, cobalt, nickel, copper, tungsten, molybdenum, and so on, from their respective metal–organic compounds.     

Reconfigurable Optical Add‐Drop Multiplexer Using a Polymer Integrated Photonic Lightwave Circuit

We have developed a fully functional reconfigurable optical add‐drop multiplexer (ROADM) switch module using a polymer integrated photonic lightwave circuit technology. The polymer variable optical attenuator (VOA) array and digital optical switch array are integrated into one polymer PLC chip and packaged to form a 10‐channel VOA integrated optical switch module. Four of these optical switch modules are used in the ROADM switch module to execute 40‐channel switching and power equalization. As a wavelength division multiplexer (WDM) filter device, two C‐band 40‐channel athermal arrayed waveguide grating WDMs are used in the ROADM module. Optical power monitoring of each channel is carried out using a 5% tap PD. A controller and firmware having the functions of a 40‐channel switch and VOA control, optical power monitoring, as well as TEC temperature control, and data communication interfaces are also developed in this study.     

Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

Realization of 2-D Variable IIR Digital Filter Structures with a Small Amount of Calculations for Coefficient Update

This paper proposes 2-D variable IIR digital filter structures with a small amount of calculations for coefficient update. The proposed realization method uses the 2-D parallel allpass structure derived from the separable denominator 2-D filter as the prototype structure for 2-D variable digital filters. In order to reduce the amount of calculations, all the redundant first-order complex allpass sections are combined by modularization of the variable structure. Furthermore, we can realize a very compact variable structure with a minimal number of first-order complex allpass sections by combining complex allpass sections with their complex conjugate allpass sections. Comparison of the calculation loads of the variable structures is presented to demonstrate that the amount of calculations for coefficient update of the proposed variable structure is far less than that of the original and the modular variable structure.     

Chiroptical‐Conjugated Polymer/Chiral Small Molecule Hybrid Thin Films for Circularly Polarized Light‐Detecting Heterojunction Devices

Herein, a simple and facile strategy is described to obtain chiroptically active semiconductor thin films by blending of poly(3‐alkylthiophene)s, which are conventional achiral polymer semiconductors, and 1,1′‐binaphthyl (BN), a versatile chiral molecule. As expected, the intermolecular interaction between the two materials is important to extend the chirality of the binaphthyl molecules to the hybrid films. The controlled phase separation and crystallization of poly[3‐(6‐carboxyhexyl)thiophene‐2,5‐diyl] (P3CT) and binaphthyl hybrid films result in unique heterojunction bilayer thin‐film structures that consisted of BN microcrystals at the top and a P3CT/BN mixed layer at the bottom. Such heterojunction bilayer films exhibit significantly amplified chiroptical response with weak broadened tails, which is due to the enhanced crystallization of the chiral BN molecules and formation of heteroaggregates in the hybrid films. Based on the characterization of crystalline structure and photoluminescence analysis, it is found that new electronic energy states are formed in the conduction band region of P3CTs in the P3CT/BN heteroaggregates, which contribute to chirality transfer from BN to the hybrid films. As a proof of concept, a photodiode capable of distinguishably sensing the left‐ and right‐handed circularly polarized light is successfully fabricated by using the hybrid films with the heterojunction bilayer structure.     

Spectrum‐Based Color Reproduction Algorithm for Makeup Simulation of 3D Facial Avatar

Various simulation applications for hair, clothing, and makeup of a 3D avatar can provide more useful information to users before they select a hairstyle, clothes, or cosmetics. To enhance their reality, the shapes, textures, and colors of the avatars should be similar to those found in the real world. For a more realistic 3D avatar color reproduction, this paper proposes a spectrum‐based color reproduction algorithm and color management process with respect to the implementation of the algorithm. First, a makeup color reproduction model is estimated by analyzing the measured spectral reflectance of the skin samples before and after applying the makeup. To implement the model for a makeup simulation system, the color management process controls all color information of the 3D facial avatar during the 3D scanning, modeling, and rendering stages. During 3D scanning with a multicamera system, spectrum‐based camera calibration and characterization are performed to estimate the spectrum data. During the virtual makeup process, the spectrum data of the 3D facial avatar is modified based on the makeup color reproduction model. Finally, during 3D rendering, the estimated spectrum is converted into RGB data through gamut mapping and display characterization.     

Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N₂ and N₂-H₂ (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N₂-H₂ environment are found to have lowest oxide trap charge density shift, ΔN_ot = 8.56 × 10¹¹ cm⁻², and the lowest interface-trap density increase, ΔN_it = 4.49 × 10¹¹ cm⁻² among the three samples as-deposited, annealed in N₂ and N₂-H₂ environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D_it = 0.834 × 10¹¹ eV⁻¹ cm⁻², using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N₂-H₂ environment after the RTA.     

Forward-stepwise regression analysis for fine leak batch testing of wafer-level hermetic MEMS packages

An advanced regression scheme is proposed to analyze fine leak batch testing data of multiple MEMS packages. The scheme employs the forward-stepwise regression method to infer the information of leaky packages from a batch test data. The analysis predicts the number of leaky packages and the true leak rate of each leaky package in a progressive manner. The scheme is implemented successfully using an actual batch test data obtained from wafer-level hermetic MEMS packages. An error analysis is followed to define the applicable domain of the scheme. Advanced formulations are also suggested to extend the applicable domain.     

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t_ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V_th and of linear drain current I_dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V_th and I_dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO₂/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.