Partial adaptive nulling on a monopulse phased array antenna system

A partial phase-only nulling (PPON) algorithm has been developed and evaluated on a 496-element monopulse phased array antenna system which employs five-bit phase shifters. Using this PPON algorithm allows nulls in the far-field pattern to be steered to the desired directions for a phased array equipped with low-resolution phase shifters to perform simultaneous nulling in the sum and two difference patterns in the environment of multiple jammers. Simulated and experimental patterns are illustrated     

X-band HBT VCO with high-efficiency CB buffer amplifier

A monolithic AlGaAs-GaAs HBT VCO with common-base (CB) buffer amplifier was demonstrated at X-band. Overall efficiency of 30% was achieved with 93-mW output power at 9.8 GHz. The MMIC chip is only 1 mm×2 mm, including the monolithic varactor diode. The circuit design offers several unique advantages: (1) the CB buffer amplifier reduces the frequency-pull effect from the external load; (2) the design for the oscillation condition and the output impedance match for power are separated; and (3) the overall efficiency can be high. A step-by-step design procedure is discussed     

A PLL clock generator with 5 to 10 MHz of lock range formicroprocessors

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8-μm CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency     

A DBR laser tunable by resistive heating

A distributed Bragg reflector (DBR) laser tuned by resistive heating is presented. It has a tuning range greater than 10 nm with only a 33% reduction in output power and a 10% increase in linewidth. Its behavior is easily modeled, agreeing well with simple theory     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

1.25-Gb/s Operation at 50-GHz Channel Spacing Based on Intensity Noise Suppression of Wavelength-Locked Fabry–PÉrot Laser Diode

We demonstrate 1.25-Gb/s operation at 50-GHz channel spacing and 10-km single-mode fiber, which is based on a wavelength-locked Fabry-Perot laser diode (F-P LD) and an intensity noise suppression by a gain saturation of F-P LD in front of the receiver. The wavelength-locked F-P LD employs the spectrum-sliced incoherent light with narrow bandwidth of 35 GHz. The intensity noise of wavelength-locked F-P LD is suppressed about 6 dB by the F-P LD in the front of the receiver. As a result, the bit-error-rate curves exhibit the error-free performances over the detuning conditions to cover a whole mode spacing period of F-P LD.     

Failure analysis of video processor defined as No Fault Found (NFF): Reproduction in system level and advanced analysis technique in IC level

This paper has studied the video processors for Flat Panel Display (FPD) which is defined as No Fault Found (NFF) among field failures. NFF phenomenon of video processor was the initial feature of field failure and showed Composite Video Broadcast Signal (CVBS) noise but it worked properly after some hours. NFF phenomenon has been a rising issue in the field of electronic device and the system recently. Highly Accelerated Life Testing (HALT) method has been used to reproduce field failure symptom. Modulated exciting technique has been applied as stress profile. Through the above, it was possible to reproduce the symptom which is the same as the field failure. Fault isolation and the defect was detected through the Advanced failure analysis method such as backside polishing, PEM, OBIRCH, and SEM. And it explains the defect and suggests the stress factor which can cause the defect.     

Nanofibrous Patches for Spinal Cord Regeneration

The difficulty in spinal cord regeneration is related to the inhibitory factors for axon growth and the lack of appropriate axon guidance in the lesion region. Here scaffolds are developed with aligned nanofibers for nerve guidance and drug delivery in the spinal cord. Blended polymers including poly(L ‐lactic acid) (PLLA) and poly(lactide‐co‐glycolide) (PLGA) are used to electrospin nanofibrous scaffolds with a two‐layer structure: aligned nanofibers in the inner layer and random nanofibers in the outer layer. Rolipram, a small molecule that can enhance cAMP (cyclic adenosine monophosphate) activity in neurons and suppress inflammatory responses, is immobilized onto nanofibers. To test the therapeutic effects of nanofibrous scaffolds, the nanofibrous scaffolds loaded with rolipram are used to bridge the hemisection lesion in 8‐week old athymic rats. The scaffolds with rolipram increase axon growth through the scaffolds and in the lesion, promote angiogenesis through the scaffold, and decrease the population of astrocytes and chondroitin sulfate proteoglycans in the lesion. Locomotor scale rating analysis shows that the scaffolds with rolipram significantly improved hindlimb function after 3 weeks. This study demonstrates that nanofibrous scaffolds offer a valuable platform for drug delivery for spinal cord regeneration.     

Performance of Hybrid Laser Diodes Consisting of Silicon Slab and InP/InGaAsP Deep‐Ridge Waveguides

The fundamental transverse mode lasing of a hybrid laser diode is a prerequisite for efficient coupling to a single‐mode silicon waveguide, which is necessary for a wavelength‐division multiplexing silicon interconnection. We investigate the lasing mode profile for a hybrid laser diode consisting of silicon slab and InP/InGaAsP deep ridge waveguides. When the thickness of the top silicon is 220 nm, the fundamental transverse mode is lasing in spite of the wide waveguide width of 3.7µm. The threshold current is 40 mA, and the maximum output power is 5 mW under CW current operation. In the case of a thick top silicon layer (1 µm), the higher modes are lasing. There is no significant difference in the thermal resistance of the two devices.