VLSI array algorithms and architectures for RSA modularmultiplication

We present two novel iterative algorithms and their array structures for integer modular multiplication. The algorithms are designed for Rivest-Shamir-Adelman (RSA) cryptography and are based on the familiar iterative Horner's rule, but use precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline. Both algorithms use a carry save adder scheme with module reduction performed on each intermediate partial product which results in an output in carry-save format. Regularity and local connections make both algorithms suitable for high-performance array implementation in FPGA's or deep submicron VLSI. The processing nodes consist of just one or two full adders and a simple multiplexor. The stored complement numbers need to be precalculated only when the modulus is changed, thus not affecting the performance of the main computation. In both cases, there exists a bit-level systolic schedule, which means the array can be fully pipelined for high performance and can also easily be mapped to linear arrays for various space/time tradeoffs     

CDMA Mobile System Testbed and Field Test

This paper briefly explains the configuration of CDMA Mobile System (CMS) test bed. The measured fading and delay results of CDMA signal in Taejon area are shown. In comparison to other cellular systems, there are more parameters in the CDMA systems that affect system performance and capacity. We performed the optimization test of the selected parameters and present the effect of each parameter on the performance. This paper presents the capacity and performance test results of CMS. The capacity test was performed on ETRI site of three sectors in Taejon area. The performance tests include call completion rate, busy hour call attempt, and the delay characteristics of voice.     

All‐Solution‐Processed Indium‐Free Transparent Composite Electrodes based on Ag Nanowire and Metal Oxide for Thin‐Film Solar Cells

Fully solution‐processed Al‐doped ZnO/silver nanowire (AgNW)/Al‐doped ZnO/ZnO multi‐stacked composite electrodes are introduced as a transparent, conductive window layer for thin‐film solar cells. Unlike conventional sol–gel synthetic pathways, a newly developed combustion reaction‐based sol–gel chemical approach allows dense and uniform composite electrodes at temperatures as low as 200 °C. The resulting composite layer exhibits high transmittance (93.4% at 550 nm) and low sheet resistance (11.3 Ω sq^‐1), which are far superior to those of other solution‐processed transparent electrodes and are comparable to their sputtered counterparts. Conductive atomic force microscopy reveals that the multi‐stacked metal‐oxide layers embedded with the AgNWs enhance the photocarrier collection efficiency by broadening the lateral conduction range. This as‐developed composite electrode is successfully applied in Cu(In_1‐x,Ga_x)S₂ (CIGS) thin‐film solar cells and exhibits a power conversion efficiency of 11.03%. The fully solution‐processed indium‐free composite films demonstrate not only good performance as transparent electrodes but also the potential for applications in various optoelectronic and photovoltaic devices as a cost‐effective and sustainable alternative electrode.     

Control of Crystal Growth toward Scalable Fabrication of Perovskite Solar Cells

With the impressive record power conversion efficiency (PCE) of perovskite solar cells exceeding 23%, research focus now shifts onto issues closely related to commercialization. One of the critical hurdles is to minimize the cell‐to‐module PCE loss while the device is being developed on a large scale. Since a solution‐based spin‐coating process is limited to scalability, establishment of a scalable deposition process of perovskite layers is a prerequisite for large‐area perovskite solar modules. Herein, this paper reports on the recent progress of large‐area perovskite solar cells. A deeper understanding of the crystallization of perovskite films is indeed essential for large‐area perovskite film formation. Various large‐area coating methods are proposed including blade, slot‐die, evaporation, and post‐treatment, where blade‐coating and gas post‐treatment have so far demonstrated better PCEs for an area larger than 10 cm². However, PCE loss rate is estimated to be 1.4 × 10^?2% cm^?2, which is 82 and 3.5 times higher than crystalline Si (1.7 × 10^?4% cm^?2) and thin film technologies (≈4 × 10^?3% cm^?2) respectively. Therefore, minimizing PCE loss upon scaling‐up is expected to lead to PCE over 20% in case of cell efficiency of >23%.     

Improving Radio Frequency Transmission Properties of Graphene via Carrier Concentration Control toward High Frequency Transmission Line Applications

Graphene has been gradually studied as a high‐frequency transmission line material owing to high carrier mobility with frequency independence up to a few THz. However, the graphene‐based transmission lines have poor conductivity due to their low carrier concentration. Here, it is observed that the radio frequency (RF) transmission performance could be severely hampered by the defect‐induced scattering, even though the carrier concentration is increased. As a possible solution, the deposition of the amorphous carbon on the graphene is studied in the high‐frequency region up to 110 GHz. The DC resistance is reduced by as much as 60%, and the RF transmission property is also enhanced by 3 dB. Also, the amorphous carbon covered graphene shows stable performance under a harsh environment. These results prove that the carrier concentration control is an effective and a facile method to improve the transmission performance of graphene. It opens up the possibilities of using graphene as interconnects in the ultrahigh‐frequency region.     

High Areal Capacitance of N‐Doped Graphene Synthesized by Arc Discharge

The lack of cost effective, industrial‐scale production methods hinders the widespread applications of graphene materials. In spite of its applicability in the mass production of graphene flakes, arc discharge has not received considerable attention because of its inability to control the synthesis and heteroatom doping. In this study, a facile approach is proposed for improving doping efficiency in N‐doped graphene synthesis through arc discharge by utilizing anodic carbon fillers. Compared to the N‐doped graphene (1–1.5% N) synthesized via the arc process according to previous literature, the resulting graphene flakes show a remarkably increased doping level (≈3.5% N) with noticeable graphitic N enrichment, which is rarely achieved by the conventional process, while simultaneously retaining high turbostratic crystallinity. The electrolyte ion storage of synthesized materials is examined in which synthesized N‐doped graphene material exhibits a remarkable area normalized capacitance of 63 µF cm^?2. The surprisingly high areal capacitance, which is superior to that of most carbon materials, is attributed to the synergistic effect of extrinsic pseudocapacitance, high crystallinity, and abundance of exposed graphene edges. These results highlight the great potentials of N‐doped graphene flakes produced by arc discharge in graphene‐based supercapacitors, along with well‐studied active exfoliated graphene and reduced graphene oxide.     

Improvement of linewidth enhancement factor in 1.55-μmmultiple-quantum-well laser diodes

The improvement of the linewidth enhancement factor in complex-coupled laser diode (CC-LD), or loss-coupled, was confirmed by measuring the spontaneous emission spectra below threshold from the sidewall of laser diodes. In addition, the serial resistance of the device was measured. The linewidth enhancement factor is improved by the presence of a light absorbing InGaAs grating for loss coupled distributed-feedback (DFB) laser diode (LD). We report the comparison of the linewidth enhancement factors of Fabry-Perot (FP) LD, conventional DFB-LD, and loss coupled DFB-LDs     

1.04 GBd low EMI digital video interface system using small swingserial link technique

In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd     

Fast DCT algorithm with fewer multiplication stages

A novel fast DCT scheme with reduced multiplication stages and fewer additions and multiplications is proposed. The proposed algorithm is structured so that most multiplications tend to be performed at the final stage, which reduces the propagation error that could occur in the fixed-point computation. Minimisation of the multiplication stages can further decrease the error