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In this paper an adaptive optimized fast blind channel estimation using cyclic prefix supported with Space Time Block Coded Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (STBC-MIMO-OFDM) system is presented. The main aspire of our technique is to support multiple users at the same time over same frequency band based on the Multi-Carrier Code-Division Multiple Access (MC-CDMA) approach. High complexity and low convergence is the main obstacle in earlier blind channel estimation techniques. Modified flower pollination algorithm is implemented to overcome this problem. The MC-CDMA approach is utilized to implement the blind channel estimation. The proposed MC-CDMA is used to reduce the error rate included in the Blind Channel Estimation. As a part of wireless communications, time block coding technique is utilized to transmit several copies of information across the number of antennas. To develop the consistency of data transfer different received data is used and then MFPA results in lower fuel cost compared to FPA. MFPA produces better results compared with previous methods.
相似文献Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
相似文献All modern computational devices consist of ALU. With increase in complexity of software and the consistent shift of software towards parallelism, high speed processors with hardware support for time consuming operations such as multiplication would benefit. Smaller, compact devices such as IoT devices need to run software such as security software and be able to offload computation cost from the cloud. In this paper, a high speed 8-bit ALU using 18 nm FinFET technology is proposed. The arithmetic and logical unit consists of fast compute units such as Kogge Stone fast adder and Dadda multiplier along with basic logic gates. In this paper, an ALU with each compute unit optimized for speed is proposed, while responsibly consuming area. Dadda multiplier is of 8 × 8 architecture as opposed to conventional approach of 4 × 4 making it a true 8-bit ALU. Simulation and analysis is done using Cadence Virtuoso in Analog Design Environment. The transistor count of proposed design is 5298, the power consumption is 219 µW and maximum delay is 166.8 ps. The design is also expected to consume a maximum of one clock cycle for any computation.
相似文献This research article presents and describes a novel design with improved performance low power consumption threshold voltage based CMOS thermal sensor for aerospace applications. The proposed temperature sensor utilizes the change in behavior of threshold voltage of MOSFET with variation in temperature. The challenge while designing the temperature sensor was to achieve the linearize output voltage with respect to change in temperature. Process corner analysis has been done to check the robustness of the circuit while performance analysis and sensitivity of the temperature sensor have been verified in the occurrence of parasitic. The proposed temperature sensor is featured with low power consumption, less power supply voltage utilization, high performance and sensitivity with inaccuracy as low as possible. The presented temperature sensor utilizes an active area of 18 µm × 9.85 µm with 117 nW power consumption. An improved linear performance with an inaccuracy of merely − 0.01 to + 0.47 °C over a wide temperature range of − 20 to + 120 °C is presented here. The sensitivity of proposed temperature sensor is found to be as high as 0.77 mV/°C. The proposed temperature sensor is realized and tested in Cadence virtuoso mixed signal design atmosphere using 0.18 µm CMOS technology and further investigated with support of tool from Mentor graphics. The engaged area of pad-limited chip is measured to be 0.96 mm2.
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