Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

SVM-based validation of motor unit potential trains extracted by EMG signal decomposition

Motor unit potential trains (MUPTs) extracted via electromyographic (EMG) signal decomposition can aid in the diagnosis of neuromuscular disorders and the study of the neural control of movement, but only if they are valid. In this paper, support vector machine (SVM)-based supervised classifiers are proposed to estimate the validity of extracted MUPTs. The classifiers use either the MU firing pattern or the MUP shape consistency of an MUPT, or both, to estimate its validity. The developed classifiers estimate the class label of an MUPT (i.e., valid/invalid) and a degree of support for the decision being made. A single SVM that estimates the validity of a given MUPT using extracted MU firing pattern and MUP shape features was investigated. In addition, the effectiveness of multiclassifier techniques which estimate the overall validity of a train by fusing the MU firing pattern and MUP shape validity of a given MUPT, determined separately by two distinct SVMs, was also investigated. Training based only on simulated data showed robust classification performance of the several multiclassifier methods when tested using both simulated and real test data. Of the methods studied, the multiclassifier constructed using trainable logistic regression to aggregate base classifier outputs had the best performance. Assuming 12.7% of extracted MUPTs are on average invalid, the estimated accuracy for this method in correctly categorizing MUPTs extracted during decomposition was 99.4% and 98.8% for simulated and real data, respectively.     

Design of an Ultra-Wideband Microstrip Patch Antenna Suspended by Shorting Pins

Designing a compact wideband microstrip patch antenna which is composed of a folded-patch feed, a symmetric E-shaped edge and shorting pins is presented in this paper. One pin is applied in order to expand the impedance bandwidth. Two other pins are utilized to miniaturize the size of patch as well. The measured impedance bandwidth ( $\text{ VSWR}\le 2$ ) of the fabricated antenna is more than 90 % in the frequency range 3.92–10.67 GHz for ultra-wideband (UWB) applications. The antenna size is $0.438\lambda _{0}\times 0.365\lambda _{0}\times 0.170\lambda _{0}$ at its center operating frequency. Also, radiation patterns with acceptable stability within the bandwidth are obtained. In addition, the effects of some key parameters are investigated to describe the performance of the proposed design.     

A second-order blind source separation method for bilinear mixtures

In this paper, we are interested in the problem of Blind Source Separation using a Second-order Statistics (SOS) method in order to separate autocorrelated and mutually independent sources mixed according to a bilinear (BL) model. In this context, we propose a new approach called Bilinear Second-order Blind Source Separation, which is an extension of linear SOS methods, devoted to separate sources present in BL mixtures. These sources, called extended sources, include the actual sources and their products. We first study the statistical properties of the different extended sources, in order to verify the assumption of identifiability when the actual sources are zero-mean and when they are not. Then, we present the different steps performed in order to estimate these actual centred sources and to extract the actual mixing parameters. The obtained results using artificial mixtures of synthetic and real sources confirm the effectiveness of the new proposed approach.     

Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S₂₁) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S₂₁ is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V _dd  = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S₂₁ of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S₂₁ of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (P_DC) of 3.6 mW, the lowest P_DC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.     

Explaining the different efficiency behaviors of PHOLEDs with/without a hole injection barrier at the hole transport layer/emitter layer interface

In this work we investigate the different efficiency behaviors of the devices with and without hole injection barrier, utilizing in our investigation the archetypical 4,4′-bis(carbazol-9-yl)biphenyl:Tris(2-phenylpyridine)iridium(III) host–guest PHOLEDs system. The results show that the recombination of electrons and holes on the host material generally leads to higher device efficiency in comparison to the case where recombination happens on the guest material. The results also show that in devices where a hole injection barrier between the HTL and the host material in the EML exists, the emission mechanism gradually changes from one based on host e–h recombination to one based on guest e–h recombination as the guest concentration is increased. When host e–h recombination is dominant, although it tends to produce higher device efficiency, host e–h recombination is generally also associated with significant efficiency roll-off; the latter arises from quenching of the host triplet excitons primarily due to host–host TTA. As the concentration of the guest molecules increases and the creation of host triplet excitons subsides (since most e–h recombination occurs on the guest) host–host TTA decreases, hence also the efficiency roll-off. In such case, quenching is mostly caused by polarons residing on guest sites. At optimum guest concentrations (∼8% Vol.), a balance between host e–h recombination and guest e–h recombination is reached, and thus also minimal TTA and Triplet-Polaron Quenching. On the other hand, in devices where hole injection barrier between the HTL and the host in the EML is insignificant, emission mechanism is always based on host e–h recombination irrespective of the guest concentration, and therefore have higher efficiency and the efficiency does not depend on guest concentration. The absence of the injection barrier in these devices results in a wider recombination zone, and hence a lower exciton concentration in general, which in turn reduces host–host TTA and thus lowers efficiency roll-off. In contrast, guest–guest TTA is not found to play a significant role in device efficiency behavior.     

A 24-channel implantable neural recording based on time and frequency-division multiplexing

This paper presents a novel approach to encapsulate prerecorded neural signals in implantable neural recording microsystems. We have increased the number of channels and the reconstructed neural signal quality in the receiver by combining time-division-multiplexing (TDM) and frequency-division-multiplexing (FDM) method. Reducing the number of channels in each TDM module is the fundamental advantage of this method that leads to reduced crosstalk noise. We evaluate some possible configurations and propose an optimized system that has less power dissipation and area occupation than other configurations. A 24-channel implantable neural recording based on the optimized system is designed in both system and circuit level. In this system, first, channels are divided into three 8-channel groups then after multiplexing in the time domain, they are combined together by FDM method. Finally, a frequency modulator wirelessly transmits neural signals to an external setup. In addition, we adjust local carrier frequencies and the bandwidth of TDM to synchronize detection without transmitting pilot carrier. To justify the system operation, using 0.18 μm CMOS technology, we design the system in circuit level. The designed circuit consumes a power of 1.39 mW at a supply voltage of 1.8 V. This leads to a power consumption of 58 μW per channel.     

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).     

Energy efficiency optimization of one-way and two-way DF relaying considering circuit power

In this paper, the energy efficiency (EE) of a decode and forward (DF) relay system is studied, where two sources communicate through a half-duplex relay node in one-way and two-way relaying strategies. Both the circuitry power and the transmission power of all nodes are taken into consideration. In addition, three different coding schemes for two-way DF relaying strategy with two phases and two-way DF relaying with three phases are considered. The aim is to maximize the EE of the system for a constant spectral efficiency (SE). For this purpose, the transmission time and the transmission power of each node are optimized. Simulations are used to compare the EE–SE curve of different DF strategies with one-way and two-way amplify and forward (AF) strategies and direct transmission (DT), to find the best energy efficient strategy in different SE conditions. Analytical and simulation results demonstrate that in low SE conditions, DF relaying strategies are more energy efficient compared to that of AF strategies and DT. However, in high SE conditions, the EE of two-way AF relaying and DT strategy outperform some of the DF relaying strategies. In simulations, the impact of different circuitry power and different channel conditions on the EE–SE curves are also investigated.