Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

A highly robust process integration with scaled ONO interpolydielectrics for embedded nonvolatile memory applications

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides     

Numerical Stability Verification of a Two-Dimensional Time-Dependent Nonlinear Shallow Water System Using Multidimensional Wave Digital Filtering Network

This paper aims to study the stability effects of a two-dimensional time-dependent nonlinear shallow water (NLSW) system based on the concordance analysis of necessary and sufficient conditions derived from a multidimensional wave digital filtering (MDWDF) network. Approximating the differential equations used to describe elements of a MD passive electrical circuit by grid-based difference equations, the satisfactory Courant–Friedrichs–Levy condition usually known to be necessary are derived with various initial conditions to provide theoretical support for the existence of a MD passive dynamical system and thus stability of the discrete equivalent. Together with the evaluation of the system’s energy and hence solution error propagation that both arise directly and sufficiently to the stability of MDWDF networks, the numerical convergence of the network can be fully established. As a consequence, all instability related aspects in relation to computational errors and overflow corrections are fully excluded leading to uniquely a high degree of robustness of MDWDF architecture. Feasible comparisons are made with a finite element method implemented in the COMSOL Multiphysics to confirm the verification process.     

Image Restoration Using Hybrid Features Improvement on Morphological Component Analysis

Images are generally corrupted by impulse noise during acquisition and transmission. Noise deteriorates the quality of images. To remove corruption noise, we propose a hybrid approach to restoring a random noise-corrupted image, including a block matching 3D (BM3D) method, an adaptive non-local mean (ANLM) scheme, and the K-singular value decomposition (K-SVD) algorithm. In the proposed method, we employ the morphological component analysis (MCA) to decompose an image into the texture, structure, and edge parts. Then, the BM3D method, ANLM scheme, and K-SVD algorithm are utilized to eliminate noise in the texture, structure, and edge parts of the image, respectively. Experimental results show that the proposed approach can effectively remove interference random noise in different parts; meanwhile, the deteriorated image is able to be reconstructed well.     

Device modeling of ferroelectric memory field-effect transistor (FeMFET)

A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.     

Cross-Interaction Between Au/Sn and Cu/Sn Interfacial Reactions

The cross-interaction between Sn/Cu and Sn/Au interfacial reactions in an Au/Sn/Cu sandwich structure was studied. Field-emission electron probe microanalysis (FE-EPMA) revealed that the Cu content in the three Au-Sn phases (AuSn, AuSn₂, and AuSn₄) was very low, less than 1 at.%. This means␣that Cu from the opposite Cu foil did not participate in the interfacial reaction at the Sn/Au interface. On the opposite Sn/Cu side, Au-substituted (Cu,Au)₆Sn₅ formed within the initial 1 min of reflow. With prolonged reflow, the Au content in the Au-substituted (Cu,Au)₆Sn₅ increased and it transformed into a Cu-substituted (Au,Cu)Sn phase with 25 at.% Cu after 1 min of reflow at 250°C. The x-ray diffraction (XRD) pattern confirmed the phase transformation of Au-substituted (Cu,Au)₆Sn₅ to Cu-substituted (Au,Cu)Sn phase. In addition, there was greater Au consumption in the Au/Sn/Cu sandwich joint structure than in the single Au/Sn reaction case, due to some of the Au participating in the opposite Sn/Cu interfacial reaction.     

Electron beam lithography in nanoscale fabrication: recent development

Miniaturization is the central theme in modern fabrication technology. Many of the components used in modern products are getting smaller and smaller. In this paper, the recent development of the electron beam lithography technique is reviewed with an emphasis on fabricating devices at the nanometer scale. Because of its very short wavelength and reasonable energy density characteristics, e-beam lithography has the ability to fabricate patterns having nanometer feature sizes. As a result, many nanoscale devices have been successfully fabricated by this technique. Following an introduction of this technique, recent developments in processing, tooling, resist, and pattern controlling are separately examined and discussed. Examples of nanodevices made by several different e-beam lithographic schemes are given, to illustrate the versatility and advancement of the e-beam lithography technique. Finally, future trends in this technique are discussed.     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

A novel dynamic Multiple Ring-based Local Restoration for point-to-multipoint multicast traffic in WDM mesh networks

Optical networks with DWDM (Dense Wavelength Division Multiplex) can provide multiple data channels to supply high speed, high capacity to perform bandwidth-intensive multicast transmission service. Light-tree is a popular technique applied to support point-to-multipoint multicast services. Any failure during a multicast session would cause severe service loss or disruptions, especially when the faults occur near the source node. A novel ring-based local fault recovery mechanism, Multiple Ring-based Local Restoration (MRLR), for point-to-multipoint multicast traffic based on the minimum spanning tree (MST) in WDM mesh networks is proposed in this article. The MRLR mechanism dismembers the multicast tree into several disjoint segment-blocks (sub-trees) and reserves preplanned spare capacity to set up multiple protection rings in each segment-block for providing rapid local recovery. The MRLR scheme outperforms other methodologies in terms of the blocking probability, recovery time, and average hop count of protection path per session for different network topologies.     

Acoustooptic Coherent Mode Coupling in Polarization-Maintaining Fiber and Its Application as a Variable-Polarization-Dependent Loss Element

In this letter, we investigate coherent acoustooptic coherent mode coupling from the LP₀₁ core mode to LP_1m cladding mode of a polarization-maintaining fiber (PMF) induced by two acoustic gratings. We show narrowband variable attenuation along either birefringent axis of the PMF by varying the relative phase between the two acoustic gratings. By launching two acoustic gratings at different frequencies, variable attenuation and low crosstalk along either birefringent axis within the acoustooptic coupling bandwidth are demonstrated