Abstract— An integral floating display (IFD) with a long depth range without floating lens distortion is proposed. Two lenses were used to reduce barrel distortion of the floating lens and three‐dimensional (3‐D) image deformation from object‐dependent longitudinal and lateral magnifications in the floating‐display system, combined with an integral imaging display. The distance between the floating lenses is the sum of their focal lengths. In the proposed configuration, lateral and longitudinal magnifications are constant regardless of the distance of the integrated 3‐D images, so the distortions from the distant‐dependent magnifications of the floating lens do not occur with the proposed method. In addition, the proposed floating system expands the depth range of the integral imaging display. As a result, the display can show a correct 3‐D floating image with a large depth range. Experimental results demonstrate that the proposed method successfully displays a 3‐D image without floating lens distortions across a large depth range. 相似文献
This work presents a simple and versatile route to produce macroporous p-type metal oxide thin films. Two-dimensional arrays of p-type NiO films with a hollow hemisphere structure were fabricated by colloidal templating and RF-sputtering followed by a subsequent heat treatment. The diameter and shell thickness of the NiO hemisphere were 800 nm and 20 nm, respectively. X-ray diffraction and high-resolution transmission electron microscopy analysis indicate that the pure NiO phase with grain size of 10 nm was obtained at calcination temperatures that exceeded 450 °C. Close-packed arrays of hollow NiO hemispheres were found to exhibit p-type gas sensing properties against (CO, H2, C3H8, CH4, NO2, and C2H5OH), leading to significantly enhanced responses to C2H5OH (Rgas/Rair = 5.0 at 200 ppm). 相似文献
This paper presents a method of autonomous topological modeling and localization in a home environment using only low-cost
sonar sensors. The topological model is extracted from a grid map using cell decomposition and normalized graph cut. The autonomous
topological modeling involves the incremental extraction of a subregion without predefining the number of subregions. A method
of topological localization based on this topological model is proposed wherein a current local grid map is compared with
the original grid map. The localization is accomplished by obtaining a node probability from a relative motion model and rotational
invariant grid-map matching. The proposed method extracts a well-structured topological model of the environment, and the
localization provides reliable node probability even when presented with sparse and uncertain sonar data. Experimental results
demonstrate the performance of the proposed topological modeling and localization in a real home environment. 相似文献
This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit. 相似文献
Optimization for structural crashworthiness and energy absorption has become an important topic of research attributable to its proven benefits to public safety and social economy. This paper provides a comprehensive review of the important studies on design optimization for structural crashworthiness and energy absorption. First, the design criteria used in crashworthiness and energy absorption are reviewed and the surrogate modeling to evaluate these criteria is discussed. Second, multiobjective optimization, optimization under uncertainties and topology optimization are reviewed from concepts, algorithms to applications in relation to crashworthiness. Third, the crashworthy structures are summarized, from generically novel structural configurations to industrial applications. Finally, some conclusions and recommendations are provided to enable academia and industry to become more aware of the available capabilities and recent developments in design optimization for structural crashworthiness and energy absorption.
The characteristics of the prevention of electrolytic corrosion during micro electrical discharge machining (EDM) using deionized water and high frequency bipolar pulse were investigated. Electrolytic corrosion during micro EDM using deionized water was analyzed using an equivalent electrical circuit based on the electrical double layer theory. Based on the analysis and experimental verification, a narrow positive pulse duration should be provided to the workpiece to prevent corrosion. A negative voltage with zero average applied voltage (Vavg, app) is also essential for this purpose. If Vavg, app is positive or negative, electrolytic corrosion occurs on the workpiece or tool, respectively. Micro holes and 3D structures without corrosion were successfully fabricated using a high frequency bipolar pulse with a pulse duration of 0.2?μs and a period of 1?μs, as well as Vavg, app?=?0?V. 相似文献
The purpose of this study was to investigate cortical interaction between brain regions in people with and without severe motor disability during brain-computer interface (BCI) operation through coherence analysis. Eighteen subjects, including six patients with cerebral palsy (CP) and three patients with amyotrophic lateral sclerosis (ALS), participated. The results showed (1) the existence of BCI performance difference caused by severe motor disability; (2) different coherence patterns between participants with and without severe motor disability during BCI operation and (3) effects of motor disability on cortical connections varying in the brain regions for the different frequency bands, indicating reduced cortical differentiation and specialisation. Participants with severe neuromuscular impairments, as compared with the able-bodied group, recruited more cortical regions to compensate for the difficulties caused by their motor disability, reflecting a less efficient operating strategy for the BCI task. This study demonstrated that coherence analysis can be applied to examine the ways cortical networks cooperate with each other during BCI tasks. PRACTITIONER SUMMARY: Few studies have investigated the electrophysiological underpinnings of differences in BCI performance. This study contributes by assessing neuronal synchrony among brain regions. Our findings revealed that severe motor disability causes more cortical areas to be recruited to perform the BCI task, indicating reduced cortical differentiation and specialisation. 相似文献
A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in two clock cycles and powering operation in four clock cycles. It can program its number range for accurate computation flexibility of 3-D graphics pipeline and eight -region piecewise linear approximation model for logarithmic and antilogarithmic conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18-mum CMOS technology with 9-k gates. It operates at the maximum frequency of 231 MHz and consumes 2.18 mW at 1.8-V supply 相似文献