A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²     

Recording of volume hologram using a beam pattern from taperedoptical fiber

A photorefractive volume hologram was recorded and probed using light diffracted from a tapered optical fiber as a reference beam. A single-mode fiber (SMF) was chemically etched and tapered to give a complicated beam pattern, and it is shown that the tapered optical fiber can be utilized to increase the storage density of the volume hologram. Spatial selectivity of the volume hologram with this method was increased by two times compared to the normal SMF referencing, which is due to the fact that the complicated beam pattern has little correlation with its shifted version     

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period     

Wave-oriented signal processing of dispersive time-domainscattering data

Phase-space data processing is receiving increased attention because or its potential for furnishing new discriminants relating to classification and identification of targets and other scattering environments. Primary emphasis has been on time-frequency processing because of its impact on transient, especially wideband, short-pulse excitations. Here, we investigate the windowed Fourier transform, the wavelet transform, and model based superresolution algorithms within the context of a fully quantified and calibrated test problem investigated by us previously: two-dimensional (2-D) short-pulse plane wave scattering by a finite periodic array of perfectly conducting coplanar flat strips. Because the forward problem has been fully calibrated and parametrized, some quantitative measures can be assigned with respect to the tradeoffs of these time-frequency algorithms, yielding tentative performance assessments of the tested processing algorithms     

Polymeric 2/spl times/2 electrooptic switch consisting of asymmetric Y junctions and Mach-Zehnder interferometer

2/spl times/2 electrooptic switches consisting of a pair of asymmetric Y junctions and Mach-Zehnder interferometer have been demonstrated in polymeric waveguides. The switching voltage is 15 V with 1.5 cm long electrode for TM polarized light at 1.3 /spl mu/m. When the branching angle of the asymmetric Y junction is 0.2/spl deg/, crosstalk of -27 to -22 dB are obtained for both input arms. The measured insertion loss by the lens coupling is about 9-10 dB.     

A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-μm CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation     

Efficient performance analysis of asynchronous cellular CDMA overRayleigh-fading channels

The bit error rate (BER) analysis of a direct-sequence code-division multiple-access (DS-CDMA) cellular system over a Rayleigh-fading channel often results in complicated expressions even though the Gaussian approximation is applied. A combined probability density function (pdf) approach for the forward link and a mean-method technique for the reverse link are proposed to significantly reduce the computational complexity. The simplified BER expressions are derived and yield accurate results     

Algorithm for mapping between information bits and channel symbolsin MTCM codes

An algorithm for mapping between information bits and channel symbols in multiple trellis-coded modulation (MTCM) codes with M-PSK signal sets is proposed. The core of the algorithm assigns information bits with a Hamming distance in proportion to the sum of the Euclidean distance to each M-PSK symbol. The analytical results show that the additional gains from applying the algorithm can be achieved with little or no loss     

Integrated-Optic Polarization Controlling Devices Using Electro-Optic Polymers

Integrated-optic polarization controlling devices such as polarizers, polarization splitters, and polarization converters, are proposed and demonstrated in nonlinear optic polymers. Poling-induced birefringence in electro-optic polymers is exploited to fabricate the devices. The polymeric waveguide polarizers show low excess losses, and extinction ratios of 20.7 dB and 17.1 dB for TM-pass and TE-pass polarizers, respectively. The polymeric waveguide polarization splitters exhibit TE-TM mode splittings with crosstalk of 14.2 dB and 10.1 dB for TM and TE mode splittings, respectively. The polymeric waveguide polarization converters show successful TE/TM polarization mode conversion with conversion efficiencies of higher than 30 dB. The device employs poling-induced waveguides which have slowly rotating azimuth angle of optic axis along the light propagation direction. The novel polarization converter is insensitive to wavelength and easier to fabricate than the other polarization converters containing periodic structures.     

A Time‐Constrained Information Processing Model in Ubiquitous Environments

As pervasive computing is widely adopted and reliable networks are becoming more easily accessible, there is a rapidly growing need to develop a mechanism to analyze and evaluate the performance of ubiquitous environments. This paper presents an information processing model which characterizes a ubiquitous environment where a variety of pieces of information need to be exchanged among devices within a system. The proposed model not only provides analytical tools to evaluate the performance of devices, but also makes it possible to identify key factors in designing a ubiquitous environment. For illustrative purposes, a test bed is constructed and the performance of the system is assessed based on the proposed model.