Characterization of centrifugally atomized Al-12Si-5Fe-3Cu-1Mg(wt%) alloy powder and extruded rod

The Al-12Si-5Fe-3Cu-1Mg(wt%) alloy was rapidly solidified by centrifugal atomization. The microstructural characteristics of rapidly solidified powder and the microstructure changes with heat treatment were investigated in terms and related to powder size. The microstructures of the powder consisted of dendritic -Al, eutectic phase, Cu-rich phase, and needle-like intermetallic compounds. These phases were much finer than that of ingot cast structure and the size decreased with increasing cooling rate. The X-ray diffraction of the atomized powders revealed the presence of non-equilibrium 3-(AlFeSi) intermetallic phase. This phase appeared to transform to an equilibrium -(AlFeSi) phase by heating at temperatures above 470°C. The extruded rod which was hot extruded at 360°C with an extrusion ratio of 40:1 also revealed the presence of the -(AIFeSi) intermetallic phase. Using DSC, the exothermic peak due to precipitation from the supersaturated -Al matrix was observed in the range of 200–250°C during continuous heating of atomized powder, and the size of the peaks increased with decreasing powder size.     

Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach

Simulation is indispensable in computer architecture research. Researchers increasingly resort to detailed architecture simulators to identify performance bottlenecks, analyze interactions among different hardware and software components, and measure the impact of new design ideas on the system performance. However, the slow speed of conventional execution‐driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper describes a novel fast multicore processor architecture simulation framework called Two‐Phase Trace‐driven Simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace simulation phase. Much of the simulation overhead caused by uninteresting architectural events is only incurred once during the cycle‐accurate simulation‐based trace generation phase and can be omitted in the repeated trace‐driven simulations. We report our experiences with tsim, an event‐driven multicore processor architecture simulator that models detailed memory hierarchy, interconnect, and coherence protocol based on the TPTS framework. By applying aggressive event filtering, tsim achieves an impressive simulation speed of 146 millions of simulated instructions per second, when running 16‐thread parallel applications. Copyright © 2010 John Wiley & Sons, Ltd.     

The Effectiveness of Short Message Service for Communication With Concerns of Privacy Protection and Conflict Avoidance

Why would people use Short Message Service (SMS) to say something they would not say in person? There is a trend that SMS is becoming more and more popular because it facilitates more extended modes of communications. Using technology acceptance model, we hypothesize the attitude of SMS would be influenced by its perceived effectiveness for communications, perceived ease of use, and subjective norm. Besides the special aspects of communications, conflict avoidance and privacy protection will enforce the impact of perceived effectiveness of SMS for communication. We investigated 953 SMS users and the results support most of our hypotheses. Furthermore, our analyses also show there are differences between females and males on the influence mechanism behind their attitude towards SMS.     

Buffer management in a real-time shared disks cluster

A great deal of research indicates that the shared disks (SD) cluster is suitable to high performance transaction processing. However, the aggregation of SD cluster with real-time processing has not been investigated. By adopting cluster technology, the real-time services will be highly available and can exploit internode parallelism. In this paper, we consider buffer management issues in a real-time SD cluster. We first propose a real-time buffer coherency algorithm that exploits inherent characteristics of real-time applications and SD cluster. Then we extend traditional buffer replacement algorithms to the real-time SD cluster. They emphasize specific attributes of buffer pages to capitalize locality of references, transaction deadline, and affinity-based routing. We evaluate the performance of the proposed algorithms under a wide variety of transaction workloads and system configurations.     

A comprehensive survey on functional link neural networks and an adaptive PSO–BP learning for CFLNN

This paper proposed a hybrid genetic based functional link artificial neural network (HFLANN) with simultaneous optimization of input features for the purpose of solving the problem of classification in data mining. The aim of the proposed approach is to choose an optimal subset of input features using genetic algorithm by eliminating features with little or no predictive information and increase the comprehensibility of resulting HFLANN. Using the functionally expanded of selected features, HFLANN overcomes the nonlinearity nature of problems, which is commonly encountered in single-layer neural networks. The features like simplicity of the architecture and low computational complexity of the network encourage us to use it in classification task of data mining. Further, the issue of statistical tests for comparison of algorithms on multiple datasets, which is even more essential to typical machine learning and data mining studies, has been all but ignored. In this work, we recommend a set of simple, yet safe and robust parametric and nonparametric tests for statistical comparisons of HFLANN with FLANN and RBF classifiers over multiple datasets by an extensive simulation studies.     

Emergent self-organizing feature map for recognizing road sign images

Road sign recognition system remains a challenging part of designing an Intelligent Driving Support System. While there exist many approaches to classify road signs, none have adopted an unsupervised approach. This paper proposes a way of Self-Organizing feature mapping for recognizing a road sign. The emergent self-organizing map (ESOM) is employed for the feature mapping in this study. It has the capability of visualizing the distance structures as well as the density structure of high-dimensional data sets, in which the ESOM is suitable to detect non-trivial cluster structures. This paper discusses the usage of ESOM for road sign detection and classification. The benchmarking against some other commonly used classifiers was performed. The results demonstrate that the ESOM approach outperforms the others in conducting the same simulations of the road sign recognition. We further demonstrate that the result obtained with ESOM is significantly more superior than traditional SOM which does not take into the boundary effect like ESOM did.     

Two versions of architectures for dynamic implied addressing mode

The complexity of today’s embedded applications increases with various requirements such as execution time, code size or power consumption. To satisfy these requirements for performance, efficient instruction set design is one of the important issues because an instruction customized for specific applications can make better performance than multiple instructions in aspect of fast execution time, decrease of code size, and low power consumption. Limited encoding space, however, does not allow adding application specific and complex instructions freely to the instruction set architecture. To resolve this problem, conventional architectures increases free space for encoding by trimming excessive bits required beyond the fixed word length. This approach however shows severe weakness in terms of the complexity of compiler, code size and execution time. In this paper, we propose a new instruction encoding scheme based on the dynamic implied addressing mode (DIAM) to resolve limited encoding space and side-effect by trimming. We report our two versions of architectures to support our DIAM-based approach. In the first version, we use a special on-chip memory to store extra encoding information. In the second version, we replace the memory by a small on-chip buffer along with a special instruction. We also suggest a code generation algorithm to fully utilize DIAM. In our experiment, the architecture augmented with DIAM shows about 8% code size reduction and 18% speed up on average, as compared to the basic architecture without DIAM.     

Robust Calibration for Localization in Clustered Wireless Sensor Networks

This paper presents a robust calibration procedure for clustered wireless sensor networks. Accurate calibration of between-node distances is one crucial step in localizing sensor nodes in an ad-hoc sensor network. The calibration problem is formulated as a parameter estimation problem using a linear calibration model. For reducing or eliminating the unwanted influence of measurement corruptions or outliers on parameter estimation, which may be caused by sensor or communication failures, a robust regression estimator such as the least-trimmed squares (LTS) estimator is a natural choice. Despite the availability of the FAST-LTS routine in several statistical packages (e.g., R, S-PLUS, SAS), applying it to the sensor network calibration is not a simple task. To use the FAST-LTS, one needs to input a trimming parameter, which is a function of the sensor redundancy in a network. Computing the redundancy degree and subsequently solving the LTS estimation both turn out to be computationally demanding. Our research aims at utilizing some cluster structure in a network configuration in order to do robust estimation more efficiently. We present two algorithms that compute the exact value and a lower bound of the redundancy degree, respectively, and an algorithm that computes the LTS estimation. Two examples are presented to illustrate how the proposed methods help alleviate the computational demands associated with robust estimation and thus facilitate robust calibration in a sensor network.     

Modeling and simulation of powered hip orthosis by pneumatic actuators

In this study, a simulation model for a powered hip orthosis (PHO) with air muscles to predict the gait of paraplegics is presented which can be used as a design tool for hip orthoses. Before simulation, mathematical models for a human dummy with an orthosis and a pneumatic muscle actuator were generated. For the air muscle, coefficients required were obtained by static and dynamic experiments of the air muscle and experiments for the valve controlling the air pressure. The computation was conducted on the ADAMS package together with MATLAB. Computer simulation of the flexion of hip joints by the pneumatic muscle results in similar values to those from gait analysis. With the development of a simulation model for a PHO, the gait simulation model using pneumatic muscles can be used to analyze and evaluate the characteristics and efficiency of a PHO by setting the input and boundary conditions.