Performance analysis of the forward link cdma2000 1xEV‐DO evolution for multirate services in cellular wireless system

In this paper, we propose a combined analytical and simulation framework for performance evaluation of the forward link in the cdma2000 evolution for data only (1xEV‐DO) cellular systems with throughput and spectral efficiency being used as performance metrics. A closed form expression for the aggregate average throughput is derived in terms of system‐dependent parameters and a discrete random process that reflects the stochastic behavior of the transmission channel. The random process is expressed in terms of the cumulative distribution function (CDF) of the users signal‐to‐interference‐plus‐noise ratio (SINR). Quantitative results for throughput and spectral efficiency are presented for a variety of users distribution models, base station antenna types and frequency reuse factors for the cases of sectorized and non‐sectorized cells. Furthermore, we study the impact of the cell radius on the system performance. Copyright © 2006 John Wiley & Sons, Ltd.     

Low distortion CMOS transconductance amplifier

A novel low distortion CMOS linearized transconductor circuit is developed for analogue signal processing. The circuit gives a very low distortion level and a wide linearity range when compared with other reported topologies. Simulation results based on using the 0.5 µm CMOS process show that this approach gives an exceptional linearity and an excellent performance.     

A single-stage zero-voltage zero-current-switched full-bridge DCpower supply with extended load power range

A single-stage power-factor-corrected pulsewidth modulation power converter with extended load power range is presented. The topology is based on a zero-voltage zero-current-switched full-bridge (ZVZCS-FB) inverter. Steady-state analysis of the topology shows that by operating the LC load filter in discontinuous mode, the DC-link voltage remains bounded and independent of the load level. Therefore, the load power range can be further expanded, including the no-load operating condition. The analysis also shows that the extension of the load power range is achieved without any penalty in: (1) the input power factor (due to the input current waveshaping feature); (2) the power converter efficiency (due to ZVZCS and the single-stage features); and (3) the load voltage quality (due to the high bandwidth of the phase control loop). Simulated and experimental results are included to show the feasibility of the proposed scheme     

CMOS low-voltage class-AB operational transconductance amplifier

The authors present a new low-voltage class-AB operational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited for low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included     

Link budget analysis for multistandard receiver architectures

As devices shrink, creating integrated circuits (ICs) that work with the required accuracy becomes more difficult due to issues related to device physics. Receivers are part of an area referred to as "mixed-signal design," meaning that both analog and digital circuitry will be on the same IC. This too presents many challenging issues, as the analog circuitry is highly sensitive to disruptions caused by the noisy digital circuitry. Therefore, accurate modeling and simulation is crucial in the design of wireless receivers to ensure the best possible operation of the fabricated IC. Through simulation and modeling a designer can determine if receiver architecture will meet the required specifications and pinpoint the possible problems before valuable time is spent developing the actual circuit. This article will present design issues for multistandard wireless receivers to give the reader an understanding of the challenges involved in link-budget analysis. TITAN (Toolbox for Integrated Transceiver Analysis), a link-budget analysis tool developed at The Ohio State University Analog VLSI Laboratory, will be presented as an example of a tool for receiver simulation. To determine design performance, various requirements must be translated to model parameters. Among the requirements for receivers are noise floor (NF), second- and third-order distortion (IP2 and IP3, respectively), reciprocal mixing, and phase noise. TITAN offers a graphical interface and encapsulated models to the designer, eliminating the possibility of formula corruption. The interface provides a more intuitive and sophisticated way of setting up the simulation and provides the designer with more readable results. Additionally, a blocking profile component allows the architecture to be tested across multiple standards.     

Congestion‐aware multiaccess edge computing collaboration model for 5G

In 5G cloud computing, the most notable and considered design issues are the energy efficiency and delay. The majority of the recent studies were dedicated to optimizing the delay issue by leveraging the edge computing concept, while other studies directed its efforts towards realizing a green cloud by minimizing the energy consumption in the cloud. Active queue management‐based green cloud model (AGCM) as one of the recent green cloud models reduced the delay and energy consumption while maintaining a reliable throughput. Multiaccess edge computing (MEC) was established as a model for the edge computing concept and achieved remarkable enhancement to the delay issue. In this paper, we present a handoff scenario between the two cloud models, AGCM and MEC, to acquire the potential gain of such collaboration and investigate its impact on the cloud fundamental constraints; energy consumption, delay, and throughput. We examined our proposed model with simulation showing great enhancement for the delay, energy consumption, and throughput over either model when employed separately.     

Radio resource management for LTE-A relay-enhanced cells with spatial reuse and max–min fairness

One of the major issues in LTE-Advanced (LTE-A) systems is the poor capacity at the cell edge. This is mainly due to the interference experienced by the users as a result of the aggressive frequency reuse usually implemented. Relaying offers an attractive solution for this problem by offering better links than those with the eNodeB (eNB) for the terminals suffering from high path loss or high interference. However, adding relays complicates the resource allocation problem at the eNB and therefore the need for more efficient schemes arises. This is also aggravated by the reuse of resource blocks (RBs) by the relays to fully exploit the scarce spectrum, which, in turn, leads to intra-cell interference. In this paper, we study the joint power and resource allocation problem in LTE-A relay-enhanced cells that exploit spatial reuse. To guarantee fairness among users, a max–min fair optimization objective is used. This complex problem is solved using coordinate ascent and the difference of two convex functions (DC) programming techniques and the proposed scheme indeed converges to a local-optimum quickly. This is shown to be a satisfactory solution according to the simulation results that indicate an almost sevenfold increase in the 10th percentile capacity when compared to previously proposed solutions.     

On selection of forwarding nodes for long opportunistic routes

Opportunistic routing is a promising routing paradigm which increases the network throughput. It forces the sender’s neighbors, who successfully overheard the transmitted packet, to participate in the packet forwarding process as intermediate forwarding nodes. As a seminal opportunistic routing protocol, MORE combines network coding idea with opportunistic routing to eliminate the need for strict coordination among active forwarding nodes. In this paper, we show that MORE performance does not scale well with the route length, especially when the route length goes beyond two hops. Also, we found that MORE fails to establish a working opportunistic route in sparse networks. Clearly, the network throughput is directly influenced by both the quantity and quality of forwarding nodes, and their cooperation order. In this paper, we propose a new forwarder selection mechanism which considers the route length, link qualities, the distance from the source, and nodes density. It eliminates the occasional route disconnectivity happening in MORE and improves the quality of the established opportunistic routes. The simulation result indicates that our proposal always outperforms MORE when dealing with long opportunistic routes.

     

Outage Probability Analysis of Cooperative Diversity Networks Over Weibull and Weibull-Lognormal Channels

This paper presents the analysis of outage probability for a cooperative diversity wireless network using amplify-and-forward relays over independent non-identical distributed Weibull and Weibull-lognormal fading channels for single as well as multiple relays. To reach that end, a closed-from expression for the moment-generating function of the total signal-to-noise-ratio (SNR) at the destination is derived in terms of the tabulated Meijer’s G-function. Since it is hard to determine the exact probability distribution function of the SNR, a tight lower bound approximation is proposed. Simulation results are presented that show that the outage probability lower bound tends to be tight at high SNR values thus verifying the analytical results. The results also show the potential gain of relaying on the outage probability.     

Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design

Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. This paper addresses this problem using an integer linear programming (ILP) approach. Specifically, on a heterogeneous 3D CMP, it explores how applications can be mapped onto 3D ICs to maximize reliability. Preliminary experiments indicate that the proposed technique generates promising results in both reliability and performance.