Highly Crystalline Soluble Acene Crystal Arrays for Organic Transistors: Mechanism of Crystal Growth During Dip‐Coating

The preparation of uniform large‐area highly crystalline organic semiconductor thin films that show outstanding carrier mobilities remains a challenge in the field of organic electronics, including organic field‐effect transistors. Quantitative control over the drying speed during dip‐coating permits optimization of the organic semiconductor film formation, although the kinetics of crystallization at the air–solution–substrate contact line are still not well understood. Here, we report the facile one‐step growth of self‐aligning, highly crystalline soluble acene crystal arrays that exhibit excellent field‐effect mobilities (up to 1.5 cm V^?1 s^?1) via an optimized dip‐coating process. We discover that optimized acene crystals grew at a particular substrate lifting‐rate in the presence of low boiling point solvents, such as dichloromethane (b.p. of 40.0 °C) or chloroform (b.p. of 60.4 °C). Variable‐temperature dip‐coating experiments using various solvents and lift rates are performed to elucidate the crystallization behavior. This bottom‐up study of soluble acene crystal growth during dip‐coating provides conditions under which one may obtain uniform organic semiconductor crystal arrays with high crystallinity and mobilities over large substrate areas, regardless of the substrate geometry (wafer substrates or cylinder‐shaped substrates).     

An optimal checkpointing-strategy for real-time control systemsunder transient faults

Real-time computer systems are often used in harsh environments, such as aerospace, and in industry. Such systems are subject to many transient faults while in operation. Checkpointing enables a reduction in the recovery time from a transient fault by saving intermediate states of a task in a reliable storage facility, and then, on detection of a fault, restoring from a previously stored state. The interval between checkpoints affects the execution time of the task. Whereas inserting more checkpoints and reducing the interval between them reduces the reprocessing time after faults, checkpoints have associated execution costs, and inserting extra checkpoints increases the overall task execution time. Thus, a trade-off between the reprocessing time and the checkpointing overhead leads to an optimal checkpoint placement strategy that optimizes certain performance measures. Real-time control systems are characterized by a timely, and correct, execution of iterative tasks within deadlines. The reliability is the probability that a system functions according to its specification over a period of time. This paper reports on the reliability of a checkpointed real-time control system, where any errors are detected at the checkpointing time. The reliability is used as a performance measure to find the optimal checkpointing strategy. For a single-task control system, the reliability equation over a mission time is derived using the Markov model. Detecting errors at the checkpointing time makes reliability jitter with the number of checkpoints. This forces the need to apply other search algorithms to find the optimal number of checkpoints. By considering the properties of the reliability jittering, a simple algorithm is provided to find the optimal checkpoints effectively. Finally, the reliability model is extended to include multiple tasks by a task allocation algorithm     

A high-yield fabrication process for silicon neural probes

There is a great need for silicon microelectrodes that can simultaneously monitor the activity of many neurons in the brain. However, one of the existing processes for fabricating silicon microelectrodes-reactive-ion etching in combination with anisotropic KOH etching-breaks down at the wet-etching step for device release. Here we describe a modified wet-etching sidewall-protection technique for the high-yield fabrication of well-defined silicon probe structures, using a Teflon shield and low-pressure chemical vapor deposition (LPCVD) silicon nitride. In the proposed method, a micro-tab holds each individual probe to the central scaffold, allowing uniform anisotropic KOH etching. Using this approach, we obtained a well-defined probe structure without device loss during the wet-etching process. This simple method yielded more accurate fabrication and an improved mechanical profile.     

Studies on the performance characteristics and improvements of the piezoelectrically-driven micro gas compressors

This study presents the main characteristics of a micro gas compressor produced by microfabrication techniques on silicon wafers. The compressor consists of a compression chamber, check valves and a silicon membrane where the piezoelectric bimorph actuator is installed. Compressor performance was investigated under various working conditions of input voltage and frequency to the actuator at several downstream back pressures. Volume stroke ratio is a critical parameter for gas compressors. However, micro actuators do not generally produce large displacement, so the volume stroke ratio of the micro compressor is expected to be significantly less than that of conventional mechanical compressors. Therefore, the possibility of using dual compression was also investigated in order to improve micro compressor performance. The performance of the micro compressor is evaluated in this study through experiments and simulation.     

Electrically tunable dual-wavelength switching in a mutually injection-locked erbium-doped fiber ring laser and distributed-feedback laser diode

Wavelength switching in a mutually injection-locked erbium-doped fiber ring laser and distributed-feedback laser diode (DFBLD) is experimentally demonstrated. By adjusting the power and the polarization state of injected light, three stable oscillation regimes were observed: Fabry-Pe/spl acute/rot (FP) mode oscillation, main distributed-feedback (DFB) mode oscillation, and dual-wavelength oscillation. Wavelength switching of 0.8 nm from one of the FP oscillation modes to the main DFB mode of the DFBLD is accomplished when the bias current to the DFBLD is varied from 9 to 14 mA. We also show that these wavelengths can be tuned as much as 2.48 nm when the temperature of the DFBLD is changed by 20/spl deg/C.     

Automatic Transformation of Membrane‐Type Electronic Devices into Complex 3D Structures via Extrusion Shear Printing and Thermal Relaxation of Acrylonitrile–Butadiene–Styrene Frameworks

This work demonstrates a means of automatic transformation from planar electronic devices to desirable 3D forms. The method uses a spatially designed thermoplastic framework created via extrusion shear printing of acrylonitrile–butadiene–styrene (ABS) on a stress‐free ABS film, which can be laminated to a membrane‐type electronic device layer. Thermal annealing above the glass transition temperature allows stress relaxation in the printed polymer chains, resulting in an overall shape transformation of the framework. In addition, the significant reduction in the Young's modulus and the ability of the polymer chains to reflow in the rubbery state release the stress concentration in the electronic device layer, which can be positioned outside the neutral mechanical plane. Electrical analyses and mechanical simulations of a membrane‐type Au electrode and indium gallium zinc oxide transistor arrays before and after transformation confirm the versatility of this method for developing 3D electronic devices based on planar forms.     

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.     

Tunnel lane‐positioning system for autonomous driving cars using LED chromaticity and fuzzy logic system

Currently, studies on autonomous driving are being actively conducted. Vehicle positioning techniques are very important in the autonomous driving area. Currently, the global positioning system (GPS) is the most widely used technology for vehicle positioning. Although technologies such as the inertial navigation system and vision are used in combination with GPS to enhance precision, there is a limitation in measuring the lane and position in shaded areas of GPS, like tunnels. To solve such problems, this paper presents the use of LED lighting for position estimation in GPS shadow areas. This paper presents simulations in the environment of three‐lane tunnels with LEDs of different color temperatures, and the results show that position estimation is possible by the analyzing chromaticity of LED lights. To improve the precision of positioning, a fuzzy logic system is added to the location function in the literature [1]. The experimental results showed that the average error was 0.0619 cm, and verify that the performance of developed position estimation system is viable compared with previous works.     

Disclosing the Role of Defect-Engineered Metal–Organic Frameworks in Mixed Matrix Membranes for Efficient CO2 Separation: A Joint Experimental-Computational Exploration

Incorporation of defects in metal–organic frameworks (MOFs) offers new opportunities for manipulating their microporosity and functionalities. The so-called “defect engineering” has great potential to tailor the mass transport properties in MOF/polymer mixed matrix membranes (MMMs) for challenging separation applications, for example, CO₂ capture. This study first investigates the impact of MOF defects on the membrane properties of the resultant MOF/polymer MMMs for CO₂ separation. Highly porous defect-engineered UiO-66 nanoparticles are successfully synthesized and incorporated into a CO₂-philic crosslinked poly(ethylene glycol) diacrylate (PEGDA) matrix. A thorough joint experimental/simulation characterization reveals that defect-engineered UiO-66/PEGDA MMMs exhibit nearly identical filler–matrix interfacial properties regardless of the defect concentrations of their parental UiO-66 filler. In addition, non-equilibrium molecular dynamics simulations in tandem with gas transport studies disclose that the defects in MOFs provide the MMMs with ultrafast transport pathways mainly governed by diffusivity selectivity. Ultimately, MMMs containing the most defective UiO-66 show the most enhanced CO₂/N₂ separation performance—CO₂ permeability = 470 Barrer (four times higher than pure PEGDA) and maintains CO₂/N₂ selectivity = 41—which overcomes the trade-off limitation in pure polymers. The results emphasize that defect engineering in MOFs would mark a new milestone for the future development of optimized MMMs.     

Physicochemically Stable Polymer‐Coupled Oxide Dielectrics for Multipurpose Organic Electronic Applications

A chemically coupled polymer layer is introduced onto inorganic oxide dielectrics from a dilute chlorosilane‐terminated polystyrene (PS) solution. As a result of this surface modification, hydrophilic‐oxide dielectrics gain hydrophobic, physicochemically stable properties. On such PS‐coupled SiO₂ or AlO_x dielectrics, various vacuum‐ and solution‐processable organic semiconductors can develop highly ordered crystalline structures that provide higher field‐effect mobilities (μ_FETs) than other surface‐modified systems, and negligible hysteresis in organic field‐effect transistors (OFETs). In particular, the use of PS‐coupled AlO_x nanodielectrics enables a solution‐processable triethylsilylethynyl anthradithiophene OFET to operate with μ_FET ～ 1.26 cm² V^?1 s^?1 at a gate voltage below –1 V. In addition, a complementary metal‐oxide semiconductor‐like organic inverter with a high voltage gain of approximately 32 was successfully fabricated on a PS‐coupled SiO₂ dielectric.