Thermomechanical fatigue—damage mechanisms and mechanism-based life prediction methods

An existing extensive database on the isothermal and thermomechanical fatigue behaviour of high-temperature titanium alloy EVII 834 and dispersoid-strengthened aluminum alloy X8019 in SiC particle-reinforced as well as unreinv conditions was used to evaluate both the adaptability of fracture mechanics approaches to TMF and the resulting predictive capabilities of determining material life by crack propagation consideration. Selection of the correct microstructural concepts was emphasised and these concepts were, then adjusted by using data from independent experiments in order to avoid any sort of fitting. It is shown that the cyclic /-integral (δJ_eff concept) is suitable to predict the cyclic lifetime for conditions where the total crack propagation rate is approximately identical to pure fatigue crack growth velocity. In the case that crack propagation is strongly affected by creep, the creep-fatigue damage parameter δ_CF introduced by Riedel can be successfully applied. If environmental effects are very pronounced, the accelerating influence of corrosion on fatigue crack propagation can no longer implicitly be taken into account in the fatigue crack growth law. Instead, a linear combination of the crack growth rate contributions from plain fatigue (determined in vacuum) and from environmental attack is assumed and found to yield a satisfactory prediction, if the relevant corrosion process is taken into account.     

A One‐Kilobit PQR‐CMOS Smart Pixel Array

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and √T‐dependent thermal red shifts. We observed uniform bottom emissions from a 1‐kb smart pixel chip of a 32×32 InGaAs PQR laser array flip‐chip bonded to a 0.35 µm CMOS‐based PQR laser driver. The PQR‐CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

Neue Entwicklungen beim Hohlkatoden‐Gasflusssputtern. New Developments in Hollow Cathode Gas Flow Sputtering

The gas flow sputter technique was invented a few years ago particularly for the inexpensive fabrication of sophisticated ceramic layers. Meanwhile, it has matured and become increasingly powerful. Today it is on the verge of being applied in industrial fabrication processes. The present article gives an overview over the method, its characteristics and the numerous applications.     

Dynamic Survivability in WDM Mesh Networks Under Dynamic Traffic

Network survivability is a crucial requirement in WDM mesh networks. In this paper, we systematically consider the problem of dynamic survivability with dynamic single link failure in WDM networks under dynamic traffic demands. Specifically, we investigate various protection schemes, such as dedicated path protection (DPP), shared path protection (SPP), dedicated link protection (DLP), shared link protection (SLP), and two restoration schemes, path restoration (PR) and link restoration (LR). Moreover, two new shared protection methods are proposed, i.e., SRLG-based shared link protection (SRLG-SLP) and SRLG-based shared path protection (SRLG-SPP). The SRLG (shared risk link group) constraint defines the availability of protection resources to a working path, which requires that any two working paths sharing the same risk of failure (or in the same SRLG) cannot share the same protection resources. Furthermore, in our study, we consider a more practical dynamic single-link failure model, in which the link-failure-interarrival time and link-failure-holding time are considered as two independent parameters. Based on this link-failure model, extensive simulations are done to analyze and compare the dynamic survivable performance of various protection and restoration schemes. Resource utilization, protection efficiency, restoration efficiency, and service disruption ratio are employed as survivable performance metrics versus traffic load, link-failure frequency, and link-failure reparation time to evaluate the survivable performance. Many meaningful results are given. In addition, we show that the developed SRLG-SLP and SRLG-SPP protection schemes perform very well in terms of protection efficiency and service disruption ratio, while sacrificing some performance in terms of resource utilization.     

P-channel Ge/Si Hetero-nanocrystal Based MOSFET Memory

The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide T_ox=2nm and the dimensions of Si- and Ge-nanocrystal D_Si=D_Ge=5nm, the retention time of this device can reach ten years(~1×10~8s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage |V_g|=3V with respect to N-wells, respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature, is desired to obtain application in future VLSI.