Effect of hydrogen annealing on hot-carrier instability of X-Ray irradiated CMOS devices

In the very large scale integration (VLSI) technology, the need for high density and high performance integrated circuit (IC) chip demands advanced processing techniques that often result in the generation of high energy particles and photons. Frequently, the radiation damage are introduced by these energetic particles and photons during device processing. The radiation damage created by x-ray irradiation, which can often occur during metal sputtering process, has been shown to potentially enhance hot-carrier instability if the neutral traps which act as electron or hole traps in the silicon dioxide is not annealed out. In this paper, we investigate the effects of annealing using different hydrogen contents and temperatures on the device characteristics and hot carrier instability of 0.5 μm CMOS devices after 1500 mJ/cm² synchrotron x-ray irradiation. Three different annealing conditions were employed; 400° C H₂, 450° C H₂, and 400° C H₂ + N₂. It is found that for all three different hydrogen anneals the normal characteristics of irradiated CMOS devices can be effectively recovered. The hot-carrier instability of bothp- andn-channel MOSFETs are significantly enhanced after x-ray irradiation due to the creation of neutral traps and positively charged oxide traps. After high H₂ (100%) concentration anneals at 450° C, the hot-carrier instability in irradiatedn-channel devices is greatly reduced and comparable to the non-irradiated devices. Although the hot-carrier instability inp-channel devices is also significantly reduced after annealing, the threshold voltage shifts are still enhanced as compared to the devices without exposure to x-ray irradiation during maximum gate current stress. For those non-irradiated, but hydrogen-annealedp-channel devices, the hot-carrier instability was observed to be worse than the non-irradiated device without hydrogen annealing.     

Two schemes for detecting CMOS analog faults

A design-for-testability scheme for detecting CMOS analog faults was reported by Favalli et al. (see ibid., vol.25, no.5, p.1239-46, 1990). The authors propose two alternative designs, one for small circuits and another for large circuits, which require significantly less area overhead (about 1/4 to 1/3) than that of Favalli's design. With the proposed modification in the first design, the untestable problem, which occurred in Favalli's design, can be alleviated. Furthermore, the proposed schemes are also fit to be implemented in VLSI circuits     

Structural design of current-mode biquad filters

This work describes how to generate and design a novel current-mode biquad filter model using tunable multiple-output operational transconductance amplifiers and grounded capacitors (MO-OTA-Cs) for synthesizing both transmission poles and zeros. Transfer functions of low-pass, band-pass, high-pass, notch and all-pass are realized based on the filter model. The theory focuses mainly on establishing a relationship between the cascaded MO-OTA-Cs and the multiple-loop feedback matrix, which makes the structural generation and design formulas. All the filter architectures contain only grounded capacitors, which can absorb parasitic capacitances and require smaller chip areas than floating ones. The simulation results are also presented to confirm the theoretical analysis.     

Analysis and design of coplanar waveguide-fed slot antenna array

A method for analyzing and designing the slot antenna array excited by a coplanar waveguide (CPW) is presented. The slots are etched on the conducting plane of the CPW and placed in the direction perpendicular to the transmission line. Moment-method analysis and matrix-pencil approach are adopted to calculate the scattering parameters and hence the self-admittance of each slot. The mutual admittances between the slots are calculated from the formulas derived for the complementary strip dipoles based on the reciprocity theorem and via Booker's relation. Then the transmission line theory is used to calculate the input impedance of the array, and an iterative process is employed to obtain a matched design for a desired slot-voltage distribution. A four-element slot array is fabricated and measured using this design procedure. Calculated results are in good agreement with measurements     

Defect Engineering in Ambipolar Layered Materials for Mode-Regulable Nociceptor

Defect engineering represents a significant approach for atomically thick 2D semiconductor material development to explore the unique material properties and functions. Doping-induced conversion of conductive polarity is particularly beneficial for optimizing the integration of layered electronics. Here, controllable doping behavior in palladium diselenide (PdSe₂) transistor is demonstrated by manipulating its adatom-vacancy groups. The underlying mechanisms, which originate from reversible adsorption/desorption of oxygen clusters near selenide vacancy defects, are investigated systematically via their dynamic charge transfer characteristics and scanning tunneling microscope analysis. The modulated doping effect allows the PdSe₂ transistor to emulate the essential characteristics of photo nociceptor on a device level, including firing signal threshold and sensitization. Interestingly, electrostatic gating, acting as a neuromodulator, can regulate the adaptive modes in nociceptor to improve its adaptability and perceptibility to handle different danger levels. An integrated artificial nociceptor array is also designed to execute unique image processing functions, which suggests a new perspective for extension of the promise of defect engineered 2D electronics in simplified sensory systems toward use in advanced humanoid robots and artificial visual sensors.     

CMOS dual-band variable-gain amplifier for 3G-WCDMA and WLAN dual-mode RF receivers

A dual-band variable-gain amplifier (DBVGA) is presented for integrated 2.2 GHz 3G-WCDMA and 5.2 GHz WLAN transceivers. DBVGA employs a DC-and-RF current steering technique for gain control, which can minimise variations of the noise, 1 dB gain compression point, and input/output impedance when the gain is tuned. The appropriate frequency operation band of DBVGA is jointly controlled by the switched-resonator load and the input stage gate bias, resulting in high cross-band isolation and out-of-band interference rejection. All circuits except the input stages are reused for both bands to have high component reuse. A fully-integrated 0.18 mum CMOS DBVGA has been implemented to verify the proposed design     

A New Secure Authenticated Group Key Transfer Protocol

Group key transfer protocols depend on a mutually trusted key generation center (KGC) to generate group keys and transport group keys to all group members secretly. Generally, KGC encrypts group keys under another secret key shared with each user during registration. In this paper, we propose a novel secure authenticated group key transfer protocol using a linear secret sharing scheme (LSSS) and ElGamal cryptosystem, where KGC broadcasts group key information to all group members. The confidentiality of this transformation is guaranteed by this LSSS and ElGamal cryptosystem. We also provide authentication for transporting this group key. Goals and security threats of our protocol are analyzed in detail.     

Model for Increasing the Power Obtained from a Thermoelectric Generator Module

We have developed a model for finding the most efficient way of increasing the power obtained from a thermoelectric generator (TEG) module with a variety of operating conditions and limitations. The model is based on both thermoelectric principles and thermal resistance circuits, because a TEG converts heat into electricity consistent with these two theories. It is essential to take into account thermal contact resistance when estimating power generation. Thermal contact resistance causes overestimation of the measured temperature difference between the hot and cold sides of a TEG in calculation of the theoretical power generated, i.e. the theoretical power is larger than the experimental power. The ratio of the experimental open-loop voltage to the measured temperature difference, the effective Seebeck coefficient, can be used to estimate the thermal contact resistance in the model. The ratio of the effective Seebeck coefficient to the theoretical Seebeck coefficient, the Seebeck coefficient ratio, represents the contact conditions. From this ratio, a relationship between performance and different variables can be developed. The measured power generated by a TEG module (TMH400302055; Wise Life Technology, Taiwan) is consistent with the result obtained by use of the model; the relative deviation is 10%. Use of this model to evaluate the most efficient means of increasing the generated power reveals that the TEG module generates 0.14 W when the temperature difference is 25°C and the Seebeck coefficient ratio is 0.4. Several methods can be used triple the amount of power generated. For example, increasing the temperature difference to 43°C generates 0.41 W power; improving the Seebeck coefficient ratio to 0.65 increases the power to 0.39 W; simultaneously increasing the temperature difference to 34°C and improving the Seebeck coefficient ratio to 0.5 increases the power to 0.41 W. Choice of the appropriate method depends on the limitations of system, the cost, and the environment.     

Failure modes and effects analysis for high-power GaN-based light-emitting diodes package technology

In this study, nondestructive test is developed to analyze the structure failure of LED package. The relationship between thermal resistance analysis and LED package failure structure is build with T3Ster thermal transient tester and scanning electron microscope (SEM). The failure LED device with defect in the attaching layer and gap between LED chip and copper are designed advisedly. The failure factors of LED package have been measured with thermal resistance analysis and SEM cross-section images. The thermal dissipation performance of LED with defect in the attaching layer is indicated by thermal resistance analysis combined with SEM cross-section images. The blister in attaching layer results in 4.4 K/W additional thermal resistance. The gap between LED chip and copper also makes high additional thermal resistance with 8.6 K/W. Different failures of LED packages are indicated obviously using thermal transfer analysis. The LED package failure structure such as interface defect between solder and cup-shaped copper is able to forecast without destructive measurement.     

The Economical PAPR Minization Scheme for Combinative Coding Technique Applied OFDM Communication System

In this paper, we propose a new combinative scheme to combine with parity check and block coding methods for the reduction of the peak to average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) system. In the proposed schemes, the simulation results shown that Peak-to-Average Power Ratio (PAPR) can be reduced by 3.502 dB. The results of this mapped can be shown that PAPR is reduced. The principle of the scheme is illustrated with the specific example of an eight-carriers signal and its computer simulation results. All simulation results have compare with ideal channel case and AWGN case separately; both of cases are shown the PAPR reduced indeed. Do Horng Guo received his B.S. Degree in Electronic Engineering from National Taiwan Marine Science University, Keelung, Taiwan, in 1983, and M.S. Degree in Computer Communication from Northrop University, Los Angeles, USA, in 1986. He is enrolled in Ph.D program in Graduate Institute of Communication Engineering of Tatung University from 2001. His current interest includes wireless communication system and digital signal processing. Chau-Yun Hsu received his B.S. degree M.S. and Ph.D in Electrical Engineering from Tatung Institute of Technology, Taipei, Taiwan, in 1981, 1983 and 1988, respectively. He was the lecturer in Department of Electrical Engineering of Tatung University from 1983 to 1985. From 1988 to 1997, he served as the Associate professor of Tatung University. Since 1998, he has been the Chair Professor of Graduate Institute of Communication Engineering of Tatung University. Now he is also the chair of department of Electrical Engineering of Tatung University. His current interest includes Wireless Channel Model and Estimation, Machine Learning, Digital Signal Processing and Image Processing.