5G MANO自动化测试实践

工欲善其事,必先利其器。自动化测试工具就是5G时代的利器。本文针对5G时代人工测试面临的挑战,提出5G MANO自动化测试解决方案、原理、方法和流程,并结合ZTEMANO项目中的HATT自动化测试工具和自动化测试实践进行论证。自动化测试,极大的提升测试效率,输出高质量的5G产品,为运营商5G建设贡献力量。     

太阳能溴化锂吸收式空调性能测试分析

太阳能溴化锂吸收式空调制冷是解决建筑节能降耗和太阳能建筑供能推广应用的重要途径。通过对太阳能热源系统、空调机组制冷系统的性能测试,确定了太阳能吸收式空调的制冷能力和太阳能辐照、冷冻出水温度及水循环流量之间的关系。在太阳能辐照度为700 W/m2、热源供水温度在75℃以上的工况下,溴化锂吸收式空调机组的COP达到0.65左右。太阳能空调内的真空环境和溶液管理措施是影响机组制冷性能的重要因素。     

大型盛会综合指挥体系建设模式分析

本文首先分析了电信运营商在参与大型盛会通信保障任务期间搭建综合指挥体系的必要性,然后结合奥运会和世博会的差异,介绍了移动运营商在两个盛会中综合指挥体系建设模式的区别,从体系架构、事件处理原则和流程、现场团队部署、体系运转方式四个方面进行了详细的对比阐述和总结。     

Measured equation of invariance with linear tensor relation for three-dimensional scattering problems

The postulate of a linear tensor relation in the measured equation of invariance (MEI) is proposed for three-dimensional (3D) problems. As a result, all three components of the field vector to be solved are coupled in the MEI. Combined with the finite difference method, the present method is applied to the analysis of scattering by 3D conducting objects and results in a significant improvement in the accuracy of numerical results as compared to those obtained with an uncoupled linear relation.     

A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-/spl mu/m CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.     

EMS: Efficient mobile sink scheduling in wireless sensor networks

Sink scheduling, in the form of scheduling multiple sinks among the available sink sites to relieve the level of traffic burden, is shown to be a promising scheme in wireless sensor networks (WSNs). However, the problem of maximizing the network lifetime via sink scheduling remains quite a challenge since routing issues are tightly coupled. Previous approaches on this topic either suffer from poor performance due to a lack of joint considerations, or are based on relaxed constraints. Therefore, in this paper, we aim to fill in the research blanks. First, we develop a novel notation Placement Pattern (PP) to bound time-varying routes with the placement of sinks. This bounding technique transforms the problem from time domain into pattern domain, and thus, significantly decreases the problem complexity. Then, we formulate this optimization in a pattern-based way and create an efficient Column Generation (CG) based approach to solve it. Simulations not only demonstrate the efficiency of the proposed algorithm but also substantiate the importance of sink mobility for energy-constrained WSNs.     

Towards thinner and low bowing silicon solar cells: form the boron and aluminum co‐doped back surface field with thinner metallization film

Using thinner wafers can largely reduce the cost of silicon solar cells. One obstacle of using thinner wafers is that few methods can provide good dopant concentration for the back surface field (BSF) and good ohmic contact while generated only in low bowing. In this paper, we have demonstrated the screening–printing B and Al (B/Al) mixture metallization film technique, making use of the screen‐printing technique and the higher solubility of B in silicon to form a B/Al‐BSF. This technique can raise the carrier concentration in the BSF by more than one order of magnitude and reduce the back surface recombination at a low firing temperature (≤800 °C). We have also shown that through the new technique, the metallization paste thickness at the rear could be reduced largely, which however did not degrade the solar cell efficiency. All these efforts are aiming for pushing forward the application of thinner wafers. Copyright © 2011 John Wiley & Sons, Ltd.     

Estimation of Roughness-Induced Power Absorption From Measured Surface Profile Data

We present a methodology for extracting the 2D power spectral density of a statistically isotropic random rough surface from height measurements by utilizing fast Fourier-Bessel transform. We compute the additional propagation loss due to surface roughness by integrating the extracted spectral density via the formula of absorption enhancement factor. Results for a microstrip demonstrate good correlation between measured and estimated loss up to 20 GHz. It is also possible to choose a random rough surface model for the measured surface and use it to predict the roughness effect on power loss.     

Compact and Harmonic Suppression Wilkinson Power Divider With Short Circuit Anti-Coupled Line

A compact Wilkinson power divider using a short circuit anti-coupled line for harmonic suppression is presented in this letter. The structure consists of a pair of anti-coupled line short circuited by a capacitive load realized by a low impedance line. It can offer three finite attenuation poles in the stopband, while arbitrary phase shift can be obtained in the passband. Design procedures have been clearly presented. A 1.8-GHz power divider is designed, fabricated and measured for demonstration. It agreed well with the simulated results. The circuit area of the proposed divider is only 40% of that of the conventional one. Furthermore, the proposed divider has spurious pass-band suppression as high as 20dB.     

中国T-MPLS统一传送网络的控制平面需求分析

介绍了传送MPLS（T—MPLS）的发展以及标准化过程，深入分析了T—MPLS对于网络控制平面提出的需求和采用基于分组的传送机制给控制平面带来的挑战。在此基础上，基于现有的ASON／GMPLS控制平面体系，针对T—MPLS面向连接的特性，给出了未来控制平面的发展趋势，以及未来传送网的发展趋势和演进过程。