Advances in the Therapeutic Effects of Apoptotic Bodies on Systemic Diseases

Apoptosis plays an important role in development and in the maintenance of homeostasis. Apoptotic bodies (ApoBDs) are specifically generated from apoptotic cells and can contain a large variety of biological molecules, which are of great significance in intercellular communications and the regulation of phagocytes. Emerging evidence in recent years has shown that ApoBDs are essential for maintaining homeostasis, including systemic bone density and immune regulation as well as tissue regeneration. Moreover, studies have revealed the therapeutic effects of ApoBDs on systemic diseases, including cancer, atherosclerosis, diabetes, hepatic fibrosis, and wound healing, which can be used to treat potential targets. This review summarizes current research on the generation, application, and reconstruction of ApoBDs regarding their functions in cellular regulation and on systemic diseases, providing strong evidence and therapeutic strategies for further insights into related diseases.     

Effects of Sodium-Glucose Co-Transporter-2 Inhibitors on Pancreatic β-Cell Mass and Function

Sodium-glucose co-transporter-2 inhibitors (SGLT2is) not only have antihyperglycemic effects and are associated with a low risk of hypoglycemia but also have protective effects in organs, including the heart and kidneys. The pathophysiology of diabetes involves chronic hyperglycemia, which causes excessive demands on pancreatic β-cells, ultimately leading to decreases in β-cell mass and function. Because SGLT2is ameliorate hyperglycemia without acting directly on β-cells, they are thought to prevent β-cell failure by reducing glucose overload in this cell type. Several studies have shown that treatment with an SGLT2i increases β-cell proliferation and/or reduces β-cell apoptosis, resulting in the preservation of β-cell mass in animal models of diabetes. In addition, many clinical trials have shown that that SGLT2is improve β-cell function in individuals with type 2 diabetes. In this review, the preclinical and clinical data regarding the effects of SGLT2is on pancreatic β-cell mass and function are summarized and the protective effect of SGLT2is in β-cells is discussed.     

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5-mm/sup 2/ 512-Mb chip.     

A Low-Cost and Low-Power Messaging System Based on the LoRa Wireless Technology

Mobile Networks and Applications - In this paper we describe a low-cost and low-power consumption messaging system based on LoRa technology. More that one billion people worldwide cannot access...     

A 320 MFLOPS CMOS floating-point processing unit for superscalarprocessors

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 μm CMOS triple-metal-layer technology on a 61 mm² die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure