Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

Memory effect in the current-voltage characteristic of 8-hydroquinoline aluminum salt films

This letter investigated the reproducible bistable resistance switching characteristics of a single-layer organic device based on 8-hydroquinoline aluminum (Alq3) fabricated by spin coating. By controlling the ON-state current through the Alq3 films, it has been possible to achieve various resistance states of the films. In addition, the resistance of the ON-state Alq3 films also affects the threshold current and voltage to switch off the device. The independence of the current-injected direction to erase the ON state implies that the filament theory could elucidate the observed phenomenon. The ratio between low- and high-resistance states can reach five orders of magnitude, which will be a potential material for nonvolatile memory application.     

A fast measurement technique of MOSFETI/sub d/-V/sub g/ characteristics

In this letter, we developed an improved ultrafast measurement method for threshold voltage V/sub th/ measurement of MOSFETs. We demonstrate I/sub d/--V/sub g/ curve measurement within 1 /spl mu/s to extract the threshold voltage of MOSFET. Errors arising from MOSFET parasitics and measurement setup are analyzed quantitatatively. The ultrafast V/sub th/ measurement is highly needed in the investigation of gate dielectric charge trapping effect when traps with short detrapping time constants are present. Application in charge trapping measurement on HfO/sub 2/ gate dielectric is demonstrated.     

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.     

The rapid thermal processing chemical vapor deposition of silicon epitaxial films

The future of ultralarge-scale integration technology is tending toward reduced thermal processing to realize devices with higher integration densities and better performance. Rapid thermal processing chemical vapor deposition (RTPCVD) is a promising technology that can preserve the advantages of high-temperature processing without degrading the fidelity of junction profiles. Defect free, thin silicon epilayers with extremely abrupt dopant-transition profiles can be re-producibly grown by RTPCVD. Very high quality n-type and p-type heavily doped epilayers, using boron, arsenic, and phosphorus as dopants, have been grown by RTPCVD. Through superior process control and reduced thermal exposure, RTPCVD is expected to play an important part in the next generation of fabrication technology and in the development of novel silicon-based materials.     

CD56+ NK lymphomas: clinicopathological features and prognosis

Dosing regimen is an important determinant of both drug cost and patient compliance. This retrospective analysis evaluated dosing regimens and drug acquisition costs for 101 patients identified from medical records in a large metropolitan hospital as having hypertension and/or benign prostatic hyperplasia and receiving alpha-blocker therapy with either doxazosin or terazosin. Although once-daily administration is generally recommended for both drugs, 25 (38%) of 66 patients receiving terazosin were treated twice daily compared with 6 (17%) of 35 patients treated twice daily with doxazosin. This difference was statistically significant. The average (mean +/- SD) daily treatment cost per patient for all individuals receiving terazosin during the period of the record review was $1.68 +/- 0.60. For patients treated with doxazosin, the average was $0.96 +/- 0.65-a highly statistically significant result. If all 66 patients receiving terazosin had been converted to doxazosin at the beginning of the study, annual savings would have been $17,345.00. These results demonstrate the importance of reviewing actual dosing regimens. The fact that doxazosin could be administered to a significantly higher percentage of patients once daily rather than twice daily substantially decreased its cost relative to terazosin. A once-daily treatment regimen may also enhance patient compliance, thereby improving the chances of therapeutic success.     

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.     

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.     

Volumetric analysis of tumor extent in nasopharyngeal carcinoma and correlation with treatment outcome

PURPOSE: To investigate the variability of tumor volume in nasopharyngeal carcinoma using quantitative measurements of tumor bulk derived from computed tomography, and to study the prognostic value of tumor volume in comparison with other variables. METHODS AND MATERIALS: Two hundred ninety patients with newly diagnosed nasopharyngeal carcinoma were included in the study. The primary tumor volume (PTV) and nodal tumor volume (NTV) were obtained by outlining the tumor contour followed by summation of areas in sequential pretreatment computed tomography axial scans. Total tumor volume (TTV) was obtained by adding the PTV and NTV. All patients had radiotherapy as the primary treatment, 67 patients also received cisplatin-based neoadjuvant chemotheraphy. RESULTS: A large variation in tumor volume was observed, especially in advanced stage disease. The median PTV (cc) in Ho's T1, T2, and T3 disease were: 6.9 (range: 0.9-42.7), 18.8 (1.6-127.9), and 52.4 (3.3-166.8). The median TTV (cc) in Ho's stage I to IV disease were: 7.6 (range: 1.3-42.7), 19.8 (3.2-55.7), 40.7 (4.1-222.7), and 51.1 (3.1-274.7). Patients with a large PTV (>60 cc) were associated with significantly poorer local control (5-year local control rate: 56%) and disease-specific survival (5-year survival rate: 53%). In patients with a small PTV (< or =20 cc), there were no significant differences in local control among different T stages. Large NTV (>30 cc) was associated with significantly higher distant failure rate (5-year distant relapse-free survival rate: 54%) and lower disease-specific survival (5-year survival rate: 40%). In multivariate analysis, only PTV was found to be an independent factor in predicting local control. CONCLUSION: A large variation of tumor volume was present in different T stage disease of nasopharyngeal carcinoma, and PTV represents an independent prognostic factor of local control that appears to be more predictive than Ho's T stage classification.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.