A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.     

Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU

Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.     

Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

The impacts of SILC and hot carrier induced drain leakage current on the refresh time in DRAM

This paper reports the temperature dependence of SILC and hot carrier induced drain leakage current, and their impact on the refresh time in Giga-bit level DRAM with practical considerations. SILC has been found to increase as the monitoring and stress temperature increases. Due to the generation of interface states, hot carrier induced pn junction leakage current and band-to-band tunneling current have been found to increase as the monitoring temperature increases.From the simulation results of a refresh circuit for Giga-bit level DRAM, it has been found that the increase of SILC with stress time is a dominant factor in refresh failure below 373K, and the pn junction leakage current will be a dominant factor at the high elevated temperature. It has been also observed that the increase of hot carrier induced drain leakage current can be a cause for the refresh failure.     

Performance analysis of error propagation effects in the DFE for ATSC DTV receivers

The paper analyzes the error propagation phenomenon in the decision feedback equalizer (DFE) for the receivers of Advanced Television Systems Committee (ATSC) digital television (DTV) and presents the performance upper-limits of the DFE by comparing various error propagation cases and the no-error propagation case. As one approach to the performance limit, we consider a blind DFE, adopting a trellis decoder with a trace-back depth of 1 as a decision device. Through simulation, we show how much the DFE performance in ATSC DTV receivers is affected by error propagation. We found that while blind equalization is preferable to decision-directed (DD) equalization at signal-to-noise ratio (SNR) values less than 18 dB, DD equalization is superior to blind equalization at SNR values greater than 18 dB. In addition, symbol error rate curves quantitatively show that the performance difference in the DFE caused by error propagation becomes clearer at the trellis decoder following the DFE. The analysis results presented are very informative for developing equalization algorithms for ATSC DTV receivers.     

Amorphous Ta-nanocrystalline RuOx diffusion barrier for lower electrode of high density memory devices

The effects of the amount of RuO₂ added in the Ta film on the electrical properties of a Ta-RuO₂ diffusion barrier were investigated using n⁺⁺-poly-Si substrate at a temperature range of 650–800°C. For the Ta layer prepared without RuO₂ addition, Ta₂O₅ phase formed after annealing at 650°C by reaction between Ta and external oxygen, leading to a higher total resistance and a non-linear I-V curve. Meanwhile, in the case of the Ta film being deposited with RuO₂ incorporation, not only a lower total resistance and ohmic characteristics exhibited, but also the bottom electrode structure was retained up to 800°C, attributing to the formation of a conductive RuO₂ crystalline phase in the barrier film by reaction with the indiffused oxygen because of a Ta amorphous structure formed by chemially strong Ta-O or Ta-Ru-O bonds and a large amount of conductive RuO₂ added. Since a kinetic barrier for nucleation in formation of the crystalline Ta₂O₅ phase from an amorphous Ta(O) phase is much higher than that of crystalline RuO₂ phase from nanocrystalline RuO_x phase, the formation of the RuO₂ phase by reaction between the indiffused oxygen and the RuO_x nanocrystallites is kinetically more favorable than that of Ta₂O₅ phase.     

Multi-objective module placement for 3-D system-on-package

System-on-package (SOP) is a viable alternative to system-on-chip (SOC) for meeting the rigorous requirements of today's mixed-signal system integration. Thermal integrity is arguably the most crucial issue in three-dimensional (3-D) SOP due to the compact nature of the 3-D integration. In addition, the power supply noise issue becomes more serious as the supply voltage continues to decrease while the number of active devices consuming power increases. We propose a 3-D module and decap (decoupling capacitance) placement algorithm that evenly distributes the thermal profile and reduces the power supply noise. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both maximum temperature and decap amount with only small increase in area, wirelength, and runtime.     

Near‐Optimum Blind Decision Feedback Equalization for ATSC Digital Television Receivers

This paper presents a near‐optimum blind decision feedback equalizer (DFE) for the receivers of Advanced Television Systems Committee (ATSC) digital television. By adopting a modified trellis decoder (MTD) with a trace‐ back depth of 1 for the decision device in the DFE, we obtain a hardware‐efficient, blind DFE approaching the performance of an optimum DFE which has no error propagation. In the MTD, the absolute distance is used rather than the squared Euclidean distance for the computation of the branch metrics. This results in a reduction of the computational complexity over the original trellis decoding scheme. Compared to the conventional slicer, the MTD shows an outstanding performance improvement in decision error probability and is comparable to the original trellis decoder using the Euclidean distance. Reducing error propagation by use of the MTD in the DFE leads to the improvement of convergence performance in terms of convergence speed and residual error. Simulation results show that the proposed blind DFE performs much better than the blind DFE with the slicer, and the difference is prominent at the trellis decoder following the blind DFE.