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31.
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S. Zhang X. Liao L. Raniero E. Fortunato Y. Xu G. Kong H. guas I. Ferreira R. Martins 《Solar Energy Materials & Solar Cells》2006,90(18-19):3001-3008
Diphasic silicon films (nc-Si/a-Si:H) have been prepared by a new regime of plasma enhanced chemical vapour deposition in the region adjacent of phase transition from amorphous to microcrystalline state. Comparing to the conventional amorphous silicon (a-Si:H), the nc-Si/a-Si:H has higher photoconductivity (σph), better stability, and a broader light spectral response range in the longer wavelength range. It can be found from Raman spectra that there is a notable improvement in the medium range order. The blue shift for the stretching mode and red shift for the wagging mode in the IR spectra also show the variation of the microstructure. By using this kind of film as intrinsic layer, a p–i–n junction solar cell was prepared with the initial efficiency of 8.51% and a stabilized efficiency of 8.01% (AM1.5, 100 mw/cm2) at room temperature. 相似文献
33.
孔庆阳 《内燃机与动力装置》2006,(2):28-31
沼气机组发电符合当今发展循环经济,节约能源的时代要求,也会对缓解国内区域性能源紧张发挥重要作用.本文介绍了当前我国沼气生产、利用的现状,阐明了沼气的组成及其燃烧特性,论述了沼气发电机组的结构原理及其创新技术. 相似文献
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Bai-Sun Kong Joo-Sun Choi Seog-Jun Lee Kwyro Lee 《Solid-State Circuits, IEEE Journal of》1996,31(9):1267-1276
A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 μm single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic 相似文献
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针对真丝云纹印花的难度,总结了设计、放样、画稿、制版四个工序中的重点技术,特别是对电脑分色描稿、计算机电子加网制作黑白片等技术与云纹花样的印制效果进行了探索,对生产具有指导作用。 相似文献
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Ning Kong Riphagen I. Lotter M. van Rooyen P. 《Wireless Communications, IEEE Transactions on》2005,4(3):866-871
This letter presents a new optimum interference mitigating combining (OIMC) scheme for the code-division multiple-access downlink RAKE receiver. The OIMC scheme optimizes the RAKE weights and maximizes the signal-to-interference-plus-noise ratio (SINR) at the RAKE combiner output. Unlike other interference mitigation schemes, the new scheme does not need to estimate the interference or data correlation matrix (and its inverse) of the received signal to render a reliable and low complexity receiver. The OIMC scheme mitigates interference by inversely proportionately weighting the finger output by its associated interference power, while simultaneously mitigating multipath fading. The interference power is found to be directly related to the finger's associated multipath channel gain, rendering the OIMC scheme with the same order of complexity as a maximal ratio combining (MRC) scheme. Under realistic channel conditions, simulation results show that the proposed OIMC scheme always outperforms MRC with a gain of up to more than 1 dB. 相似文献
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