Implementation of a high speed frequency synthesizer employing a dual input phase accumulator

We present a new PLL based frequency synthesizer, in which we have replaced the conventional phase frequency detector and the dividers (programmable counters) with a sequential dual input phase accumulator (DIPA), consisting of a digital circuit employing adders, registers and a ladder. The main feature of the DIPA is that the two input frequencies are not required to be normalized (divided down) to the step frequency of the synthesizer. Instead, the two different high frequencies, that is the reference and the output frequency of the synthesizer, are applied directly. The DIPA samples and normalizes their phases at very high rates, calculates their phase difference, producing an output that consists of a dc component proportional to the phase difference and harmonics of the two input high frequencies. These harmonics are high frequencies and can easily be rejected by a wide bandwidth filter of the loop, without affecting the high convergence speed of the loop. Moreover, these harmonics do not generate spurs near the output frequency. The resolution of the DIPA based synthesizer depends only on the length of the digital word of the DIPA, and its convergence speed depends on the lower of the two input frequencies. The output of the DIPA is a linear function of the phase difference of the two input frequencies and its dynamic range exceeds the limit of ±2π that governs the conventional phase detectors. Thus, the proposed frequency synthesizer based on the DIPA has low phase noise, no spurs nearby the output frequency, high resolution and fast convergence rate. Additionally, the output frequency can be digitally modulated under the control of the closed loop, either by phase or frequency modulation.     

An analysis of energy efficiency investments’ environment in Greece – The potential role of JESSICA instrument

The most important constraint toward the successful implementation of the energy efficiency investments in Greece remains the absence of appropriate and competitive financial schemes. Energy efficiency improvements seems to be one of the areas that JESSICA instrument should focus on in the case of Greece, considering that energy efficiency constitutes a major component of sustainable urban development. The scope of this paper is to present, in an updating way, an analysis of energy efficiency investments’ environment in Greece as well as to examine the potential role of the JESSICA instruments, aiming to the supporting of the real implementation of energy efficiency investments in Greece. In addition, a rigid methodological note is presented for the analysis as well as evaluation of the JESSICA instruments for energy efficiency projects in Greece.     

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs. This work was supported by the project PENED ’99 ED501 funded by GSRT of the Greek Ministry of Development, and the project PRENED ’99 KE 874 funded by the Research Committee of the Democritus University of Thrace. This work was partially sponsored by a scholarship from the Public Benefit Foundation of Alexander S. Onassis (Minas Dasygenis). Nikolaos Kroupis was born in Trikala in 1976. He receiver the engineering degree and Ms.C. degree in Department of Electrical and Computer Engineering from Democritous University of Thrace, Greece, in 2000 and 2002, respectively. Since 2002 he has been a Ph.D. student at the Laboratory of Electrical and Electronic Materials Technology. His research interests are in software/hardware co-design of embedded system for signal processing applications. Nikos D. Zervas received a Diploma in Electrical & Computer Engineering from University of Patras, Greece in 1997. He received the Ph.D. degree in the Department of Electrical and Computer Engineering of the same University in 2004. His research interests are in the area of high-level, power optimization techniques and methodologies for multimedia and telecommunication applications. He has received an award from IEEE Computer Society in the context of Low-Power Design Contest of 2000 IEEE Computer Elements Mesa Workshop. Mr. Zervas is a member of the IEEE, ACM and of the Technical Chamber of Greece. Minas Dasygenis was born in Thessaloniki in 1976. He received his Diploma in Electrical and Computer Engineering in 1999, from the Democritus University of Thrace, Greece, and for his diploma Thesis he was honored by The Technical Chamber of Greece and Ericsson Hellas. In 2005, he received his PhD Degree from the Democritus University of Thrace. His research interests include low-power VLSI design of arithmetic circuits, residue number system, embedded architectures, DSPs, hardware/ software codesign and IT security. He has published more than 20 papers in international journals and conferences and he has been a principal researcher in three European research projects. Konstantinos Tatas received his degree in Electrical and Computer Engineering from the Democritus University of Thrace, Greece in 1999. He received his Ph.D. in the VLSI Design and Testing Center in the same University by June 2005. He has been employed as an RTL designer in INTRACOM SA, Greece between 2000 and 2003. His research interests include low-power VLSI design of DSP and multimedia systems, computer arithmetic, IP core design and design for reuse. Antonios Argyriou received the degree in Electrical and Computer engineering from the Democritous University of Thrace, Greece, in 2001, and the M.S. and Ph.D. degrees in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, in 2003 and 2005, respectively. His primary research interests include wireless networks, mobile computing and multimedia communications. He is a member of the IEEE and ACM. Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He is currently working as Ass. Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Greece. His research interests include low power design, parallel architectures, embedded systems design, and VLSI signal processing. He has published more than 140 papers in international journals and conferences. He was leader and principal investigator in numerous research projects funded from the Greek Government and Industry as well as the European Commission (ESPRIT II-III-IV and 5th and 6th IST). He has served as General Chair and Program Chair for the International Workshop on Power and Timing Modelling, Optimisation, and Simulation (PATMOS). He received an award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT IV). He is a member of the IEEE, the VLSI Systems and Applications Technical Committee of IEEE CAS and the ACM. Antonios Thanailakis was born in Greece on August 5, 1940. He received B.Sc. degrees in physics and electrical engineering from the University of Thessaloniki, Greece, 1964 and 1968, respectively, and the Msc. and Ph.D. Degrees in electrical engineering and electronics from UMIST, Manchester, U.K. in 1968 and 1971, respectively. He has been a Professor of Microelectronics in Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece, since 1977. He has been active in electronic device and VLSI system design research since 1968. His current research activities include microelectronic devices and VLSI systems design. He has published a great number of scientific and technical papers, as well as five textbooks. He was leader for carrying out research and development projects funded by Greece, EU, or other organizations on various topics of Microlectronics and VLSI Systems Design (e.g. NATO, ESPRIT, ACTS, STRIDE).     

Stress-induced local trap levels in Au/n-GaAs Schottky diodes with embedded InAs quantum dots

Local trap levels in Au/n-GaAs Schottky diodes with embedded InAs quantum dots, generated after a long time of the device operation, have been investigated with low-frequency noise measurements performed in the temperature range of 77-298 K and at the forward current of 30 nA. Whereas the initial devices show a pure 1/f noise behavior, after a long time of operation, recombination noise was observed at frequencies above 100 Hz, in addition to the 1/f noise at lower frequencies. Analysis of the recombination noise data obtained on structures where different GaAs cap layer thicknesses have been removed by etching allowed us to determine the activation energy of the local traps and have a rough estimation of their spatial distribution.     

Classroom furniture dimensions and anthropometric measures in primary school

The purpose of this study was to compare students' dimensions to the dimension of school furniture, in primary school, and determine whether this type of furniture is well-designed and promotes good sitting posture at school by taking into account the dimensions of the children. A total of 180 (90 male and 90 female) students, from three primary schools in Thessaloniki, Greece, participated in the study. Their ages ranged from 7 to 12 years. The following human body dimensions were measured: stature, elbow height, shoulder height, upper arm length, knee height, popliteal height and buttock-popliteal length. In addition, the dimensions were measured for four different types of chairs and five types of desks prevalent in classrooms. Finally, the anthropometric measures of the students and the furniture dimensions were compared in order to identify any incompatibility between them. The data indicate a mismatch between the students' bodily dimensions and the classroom furniture available to them. The chairs are too high and too deep and desks are also too high for the pupils. This situation has negative effects on the sitting posture of the children especially when reading and writing.     

Adaptive epileptic seizure prediction system

Current epileptic seizure "prediction" algorithms are generally based on the knowledge of seizure occurring time and analyze the electroencephalogram (EEG) recordings retrospectively. It is then obvious that, although these analyses provide evidence of brain activity changes prior to epileptic seizures, they cannot be applied to develop implantable devices for diagnostic and therapeutic purposes. In this paper, we describe an adaptive procedure to prospectively analyze continuous, long-term EEG recordings when only the occurring time of the first seizure is known. The algorithm is based on the convergence and divergence of short-term maximum Lyapunov exponents (STLmax) among critical electrode sites selected adaptively. A warning of an impending seizure is then issued. Global optimization techniques are applied for selecting the critical groups of electrode sites. The adaptive seizure prediction algorithm (ASPA) was tested in continuous 0.76 to 5.84 days intracranial EEG recordings from a group of five patients with refractory temporal lobe epilepsy. A fixed parameter setting applied to all cases predicted 82% of seizures with a false prediction rate of 0.16/h. Seizure warnings occurred an average of 71.7 min before ictal onset. Similar results were produced by dividing the available EEG recordings into half training and testing portions. Optimizing the parameters for individual patients improved sensitivity (84% overall) and reduced false prediction rate (0.12/h overall). These results indicate that ASPA can be applied to implantable devices for diagnostic and therapeutic purposes.     

On labeling in graph visualization

When visualizing graphs, it is essential to communicate the meaning of each graph object via text or graphical labels. Automatic placement of labels in a graph is an NP-Hard problem, for which efficient heuristic solutions have been recently developed. In this paper, we describe a general framework for modeling, drawing, editing, and automatic placement of labels respecting user constraints. In addition, we present the interface and the basic engine of the Graph Editor Toolkit - a family of portable graph visualization libraries designed for integration into graphical user interface application programs. This toolkit produces a high quality automated placement of labels in a graph using our framework. A brief survey of automatic label placement algorithms is also presented. Finally we describe extensions to certain existing automatic label placement algorithms, allowing their integration into this visualization tool.     

A framework for analyzing probabilistic protocols and its application to the Partial Secrets Exchange

We propose a probabilistic variant of the pi-calculus as a framework to specify randomized security protocols and their intended properties. In order to express and verify the correctness of the protocols, we develop a probabilistic version of the testing semantics. We then illustrate these concepts on an extended example: the Partial Secret Exchange, a protocol which uses a randomized primitive, the Oblivious Transfer, to achieve fairness of information exchange between two parties.     

Cost and Land Functions for Wastewater Treatment Projects: Typical Simple Linear Regression versus Fuzzy Linear Regression

This paper analyzes cost data pertinent to the municipal wastewater treatment plants (MWTP) in Greece. First, data have been collected with onsite visits and contain the land size necessary for a MWTP, the construction cost, and the operation and maintenance cost of existing wastewater treatment facilities. Second, they come from analytical budgeting of natural wastewater treatment system units. Twelve equations of the form ln?Yi = A0i+A1i?ln?Xi are estimated both with ordinary least squares (OLS) and fuzzy linear regression (FLR). The root mean square error and the mean absolute error are used as fitting measures for the comparison of the OLS with the fuzzy estimations. It is shown that the FLR did produce very similar estimates but slightly inferior to those of OLS in most of the cases for these particular datasets.