Synthesis and release of ATP by soluble mitochondrial F1 in complex with its inhibitor protein during dimethylsulfoxide-water transitions

Soluble mitochondrial F1 and F1 in complex with the natural ATPase inhibitor protein (F1-IP) catalyze the spontaneous synthesis of [gamma-32P]ATP from medium [32P]phosphate and enzyme-bound ADP when incubated in media with dimethylsulfoxide (Me2SO); under these conditions, the synthesized [gamma-32P]ATP is not released into the media, it remains tightly bound to the enzymes [Gómez-Puyou, A., Tuena de Gómez-Puyou, M. & de Meis, L. (1986) Eur. J. Biochem. 159, 133-140]. Some of the characteristics of the synthesized [gamma-32P]ATP were studied in F1 and F1-IP (ATPase activities of 70 and 1-3 micromol x min(-1) x mg(-1), respectively). In Me2SO media, gamma-phosphate of synthesized ATP in F1 or F1-IP exchanges with medium phosphate. From the rates of the exchange reaction, the half-times for hydrolysis of the synthesized ATP in F1 and F1-IP were calculated: 45 min and 58 min for F1 and F1-IP, respectively. The course that synthesized [gamma-32P]ATP follows after dilution of the Me2SO synthetic mixture with aqueous buffer was determined. After dilution, the half-life of synthesized ATP in F1 was less than 1 min. In F1-IP, ATP was also hydrolyzed, but at significantly lower rates. In F1-IP, dilution also produced release of the synthesized [gamma-32P]ATP. This was assayed by the accessibility of [gamma-32P]ATP to hexokinase. About 25% of [gamma-32P]ATP synthesized in F1-IP, but not in F1, was released into the media after dilution with aqueous buffer that contained 20 mM phosphate. Release of tightly bound ATP required the binding energy of phosphate and solvation of F1-IP, however, the particular kinetics of F1-IP were also central for medium ATP synthesis in the absence of electrochemical H+ gradients.     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Person identification using multiple cues

This paper presents a person identification system based on acoustic and visual features. The system is organized as a set of non-homogeneous classifiers whose outputs are integrated after a normalization step. In particular, two classifiers based on acoustic features and three based on visual ones provide data for an integration module whose performance is evaluated. A novel technique for the integration of multiple classifiers at an hybrid rank/measurement level is introduced using HyperBF networks. Two different methods for the rejection of an unknown person are introduced. The performance of the integrated system is shown to be superior to that of the acoustic and visual subsystems. The resulting identification system can be used to log personal access and, with minor modifications, as an identity verification system