Dynamic lightpath establishment considering four-wave mixing in multifiber WDM networks

This paper proposes a dynamic lightpath establishment scheme considering four-wave mixing (FWM) in multifiber wavelength-division multiplexed (WDM) all-optical networks. The FWM is one of the most important physical impairments to be resolved in WDM networks because the FWM induces nonlinear inter-channel crosstalk and decays the performance of WDM networks. In WDM networks, data are transmitted via lightpaths. When the effect of FWM crosstalk is large, it is highly possible that data transmission fails even if lightpaths are correctly established. The proposed scheme aims to avoid not only the blocking of lightpath establishment but also the accumulation of FWM crosstalk by means of ingenious selection of routes, wavelengths, and fibers for lightpath establishment. In the proposed scheme, a route and a wavelength are selected for each lightpath based on wavelength availability and wavelength placement of established lightpaths. Furthermore, fibers on the route are selected based on estimated FWM power. In this paper, we show the effectiveness of the proposed scheme through simulation experiments.     

Electrical Properties of Isotropic Conductive Adhesives Composed of Silicone-Based Elastomer Binders Containing Ag Particles

The electrical properties of isotropic conductive adhesives (ICAs) with two different types of silicone-based binder containing Ag particles were examined. The ICAs were printed on glass substrates in order to prepare specimens for evaluating the electrical properties. In the case of adhesives containing a denatured silicone binder, both the curing and cooling steps in the isothermal curing process generated electrical conductivity. Adhesives that were cured at 120°C to 200°C exhibited similar values of electrical resistivity regardless of the different curing temperatures. By contrast, electrical conductivity was generated only during the cooling step when adhesives containing a dimethyl methylvinyl siloxane were isothermally cured. In this case, adhesives cured above 160°C exhibited high electrical resistivity. In evaluating the temperature dependence of the electrical resistivity, we found physical annealing to have significantly different effects on these specimens. In addition, we were able to make small sensitive variations in the properties of silicone-based ICAs by controlling the isothermal annealing and thermal cycling processes.     

Phase and magnetic properties of iron oxide clusters in 20CaO·20SiO2·7Fe2O3·6FeO glasses

The annealing of 20CaO·20SiO₂·7Fe₂O₃·6FeO glasses at 973K in vacuo produced clusters of iron oxide, the shape of which was nearly spherical and the diameter distributed in the narrow range 25–115Å. The phase of clusters was identified to be Fe³⁺(Fe³⁺ _{poststagger|1.30}Fe²⁺ _{poststagger|0.55}V_0.15)·O₄ in the inverse spinel structure based upon the Mössbauer spectra and x-ray diffraction profiles. The clusters exhibited superparamagnetism and their effective anisotropy energy constant was inversely proportional to the cluster diameter. The magnetization of the glasses measured by a vibrating sample magnetometer was 7.2 × 10^-6 Wbmkg^-1 at 10 kOe at room temperature and smaller than the value calculated assuming that the whole clusters have superparamagnetism. These results suggest the pinning of spins near the cluster surface.     

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer’s operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer’s operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.     

A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment

A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under ⁸⁴Kr¹⁷⁺ exposure of 322.0 MeV at various flux condition from 1?×?10³ to 5?×?10⁵ count/cm²/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.

     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.     

Improving the photovoltaic performance of co‐evaporated Cu2ZnSnS4 thin‐film solar cells by incorporation of sodium from NaF layers

We have investigated the influence of sodium (Na) on the properties of co‐evaporated Cu₂ZnSnS₄ (CZTS) layer microstructures and solar cells. The photovoltaic performance and diode properties were improved by incorporating Na from NaF layers into the CZTS layers, while Na had a negligible effect on the microstructural properties of the layer. The best cell fabricated by using an optimal CZTS layer (Cu/(Zn + Sn) = 0.70, Zn/Sn = 1.8) yielded an active area efficiency of 5.23%. The analysis of device properties suggests that charge‐carrier recombination at CZTS/CdS interface is suppressed by intentional Na incorporation from NaF layers. Copyright © 2016 John Wiley & Sons, Ltd.     

Multiple-valued radix-2 signed-digit arithmetic circuits forhigh-performance VLSI systems

VLSI-oriented multiple-valued current-mode MOS arithmetic circuits using radix-2 signed-digit number representations are proposed. A prototype adder chip is implemented with 10-μm CMOS technology to confirm the principle of operation. A multiplication scheme using four-input current-mode wired summations for realizing a high-speed small-size multiplier is presented. The 32×32-b multiplier is composed of 18800 transistors and required fewer interconnections. The multiply time is estimated to be 45 ns by SPICE simulation in 2-μm CMOS technology. It is shown that the technology is also potentially effective for the reduction of the data-bus area in VLSI     

Adaptive control of surviving symbol replica candidates in QRM-MLD for OFDM MIMO multiplexing

This paper proposes adaptive control of the number of surviving symbol replica candidates, S/sub m/ (m denotes the stage index), based on the minimum accumulated branch metric of each stage in maximum-likelihood detection employing QR decomposition and the M-algorithm (QRM-MLD) in orthogonal frequency-division multiplexing with multiple-input-multiple-output (MIMO) multiplexing. In the proposed algorithm, S/sub m/ at the mth stage (1/spl les/m/spl les/N/sub t/, N/sub t/ is the number of transmission antenna branches) is independently controlled using the threshold value calculated from the minimum accumulated branch metric at that stage and the estimated noise power. We compared the computational complexity of QRM-MLD employing the proposed algorithm with that of conventional methods at the same average packet error rate assuming the information bit rate of 1.048 Gb/s in a 100-MHz channel bandwidth (i.e., frequency efficiency of approximately 10 bit/s/Hz) using 16QAM modulation and turbo coding with the coding rate of 8/9 in 4-by-4 MIMO multiplexing. Computer simulation results show that the average computational complexity of the branch metrics, i.e., squared Euclidian distances, of the proposed adaptive independent S/sub m/ control method is decreased to approximately 38% that of the conventional adaptive common S/sub m/ control and to approximately 30% that of the fixed S/sub m/ method (S/sub m/=M=16), assuming fair conditions such that the maximum number of surviving symbol replicas at each stage is set to M/spl circ/=16.     

A quantitative evaluation of time-independent and time-dependent deformations of lead-free and lead-containing solder alloys

A method to separate plasticity and creep is discussed for a quantitative evaluation of the plastic, transient creep, and steady-state creep deformations of solder alloys. The method of separation employs an elasto-plastic-creep constitutive model comprised of the sum of the plastic, transient creep, and steady-state creep deformations. The plastic deformation is expressed by the Ramberg-Osgood law, the steady-state creep deformation by Garofalo’s creep law, and the transient creep deformation by a model proposed here. A method to estimate the material constants in the elasto-plastic-creep constitutive model is also proposed. The method of separation of the various deformations is applied to the deformation of the lead-free solder alloy Sn/3Ag/0.5Cu and the lead-containing solder alloy Sn/37Pb to compare the differences in the plastic, transient creep, and steady-state creep deformations. The method of separation provides a powerful tool to select the optimum lead-free solder alloys for solder joints of electronic devices.