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101.
Tunnel electroresistance in ferroelectric tunnel junctions (FTJs) has attracted considerable interest, because of a promising application to nonvolatile memories. Development of ferroelectric thin‐film devices requires atomic‐scale band‐structure engineering based on depolarization‐field effects at interfaces. By using FTJs consisting of ultrathin layers of the prototypical ferroelectric BaTiO3, it is demonstrated that the surface termination of the ferroelectric in contact with a simple‐metal electrode critically affects properties of electroresistance. BaTiO3 barrier‐layers with TiO2 or BaO terminations show opposing relationships between the polarization direction and the resistance state. The resistance‐switching ratio in the junctions can be remarkably enhanced up to 105% at room temperature, by artificially controlling the fraction of BaO termination. These results are explained in terms of the termination dependence of the depolarization field that is generated by a dead layer and imperfect charge screening. The findings on the mechanism of tunnel electroresistance should lead to performance improvements in the devices based on nanoscale ferroelectrics.  相似文献   
102.
A development of 170GHz/500kW level gyrotron was carried out as R&D work of ITER. The oscillation mode is TE31,8. In a short pulse experiment, the maximum power of 750kW was achieved at 85kV/40A. The efficiency was 22%. In the depressed collector operation, 500kW/36%/50ms was obtained. The maximum efficiency of 40% was obtained at PRF=470kW whereas the power decrease by the electron trapping was observed. Pulse extension was done up to 10s at PRF=170kW with the depressed collector operation. The power was limited by the temperature increase of the output window.  相似文献   
103.
This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability  相似文献   
104.
A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure  相似文献   
105.
A 32-b 500-MHz 4-1-1-1 operation 4-Mb pipeline burst cache SRAM has been developed. In order to achieve both high bandwidth operation and short latency operation, we developed the following technologies: 1) a prefetched pipeline-burst scheme with double late-write buffers, 2) gate size reduction and a bit-line equalization by source resetting, 3) point-to-point bidirectional coding I/O's to reduce bus noise and power consumption, and 4) a three-level metal 0.25-μm CMOS process technology with six transistor memory cells  相似文献   
106.
Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm2 and an effective cell size of 1.1 μm2  相似文献   
107.
Mobile Networks and Applications - In this paper we describe a low-cost and low-power consumption messaging system based on LoRa technology. More that one billion people worldwide cannot access...  相似文献   
108.
This paper presents a novel prototype of three-phase current-fed PWM converter with a switched capacitor type resonant dc link snubber circuit, which can basically operate under a principle of zero current soft switching commutation. The optimum PWM pattern-based control scheme proposed by the authors is effectively applied for this active converter. In this paper, the steady-state operating principle of a new converter circuit treated here is described. The practical design procedure of this converter is discussed from a theoretical point of view. The feasible experiment to confirm zero current soft switching commutation of this converter is concretely implemented and evaluated herein.  相似文献   
109.
We report on the fabrication of organic photodetectors (OPD) based on isolated islands of P3HT:PCBM. Pattern transfer to the active material was done with photolithography based on non-fluorinated solvents and the excessive organic semiconductor was removed with oxygen plasma reactive ion etching. The photoresist system used was found to be benign to the P3HT:PCBM layer as confirmed by absorption, thickness and roughness measurements. Current–voltage characteristics and external quantum efficiency (EQE) remained unchanged after the patterning process. It was demonstrated that it is possible to photolithographically pattern isolated islands with 200 μm edge length with the same dark current density (<10−5 A/cm2 at −2 V bias voltage) and photocurrent density (>5 × 10−3 A/cm2 at −2 V). Furthermore, concerning the solar cell performance, the patterned, small-area devices showed power conversion efficiency of 2.1% and fill-factor of 60%. Dark current was observed to depend on the size of the remaining semiconductor island, which was demonstrated on OPDs with diameter of 50 μm. The presented results show the feasibility of fabrication of isolated devices based on organic semiconductors patterned with non-fluorinated photolithography.  相似文献   
110.
Discoveries of room‐temperature ferromagnetism (RTFM) in semiconductors hold great promise in future spintronics technologies. Unfortunately, this ferromagnetism remains poorly understood and the debate concerning the nature, carrier‐mediated versus defect‐mediated, of this ferromagnetism in semiconducting oxides is still open. Here, by using X‐ray absorption (XAS) and X‐ray magnetic circular dichroism (XMCD), it is demonstrated that the oxygen ions have a ferromagnetic response in different ZnO‐based compounds showing RTFM behavior: ZnO nanoparticles capped with organic molecules and ZnO/ZnS heterostructures. These results demonstrate the intrinsic occurrence of RTFM in these systems, and point out that it is not related to the metallic cation but it relays on the conduction band of the semiconductor.  相似文献   
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