Context-Based Network and Application Management on Seamless Networking Platform

A context-based adaptive communication system is introduced for use in heterogeneous networks. Context includes the user's presence, location, available network interfaces, network availability, network priority, communication status, terminal features, and installed applications. An experimental system was developed to clarify the feasibility of using context information to flexibly control networks and applications. The system operates on a seamless networking platform we developed for heterogeneous networks. By using contexts, the system can inform the caller and callee of applications they can access, which are available through the network before communication occurs. Changes in contexts can switch an on-going application to another during actual communication. These functions provide unprecedented styles of communication. A business scenario for a seamless networking provider is also presented. Dr. Morikawa has also been in charge of NICT's Mobile Networking Group. Masugi Inoue received his B.E. from Kyoto University in 1992 and his M.E. and D.E. from the University of Tokyo in 1994 and 1997, all in the field of Electrical Engineering. He is currently a senior researcher at the Yokosuka Radio Communications Research Center under the National Institute of Information and Communications Technology (NICT), Japan, and has been engaged in R&D on ultrahigh-speed WLANs and mobile networking. He joined the Communications Research Laboratory (CRL) of the Ministry of Posts and Telecommunications, Japan, in 1997, which was reorganized as NICT in April 2004. He was a visiting researcher at Polytechnic University in Brooklyn, New York in 2000. Khaled Mahmud received his B.Sc. (Eng.) in Electrical and Electronics Engineering from the Bangladesh University of Engineering and Technology in Dhaka in 1991. He received his M.E. and Ph.D. in the same field from Shizuoka University in Japan, in 1997 and 2000, respectively. He was a research fellow at NICT, Japan, from 2000 to 2004. He is currently an Assistant Professor in the Department of Computer Science and Engineering at North South University, Bangladesh. His research interests include modulation-demodulation techniques, software radio, mobile communication systems, wireless Internet, and IP mobility technologies. Homare Murakami received his B.E. and M.E. in Electronic Engineering from Hokkaido University in 1997 and 1999. In 2004, he received the Young Investigators Award from IEICE. He is currently a researcher at NICT's Mobile Networking Group. He is also an industrial PhD student in Aalborg University since 2003. His interest areas are naming scheme, wireless TCP and new transport protocol, IP mobility, fast handover method, and location management. Mikio Hasegawa received his B. Eng, M. Eng., and Dr. Eng. in 1995, 1997, and 2000 from Science University of Tokyo. From 1997 to 2000, he was a Research Fellow of the Japan Society for the Promotion of Science (JSPS). He is currently a senior researcher in Mobile Networking Group, National Institute of Information and Communications Technology, and a technical advisor in ChaosWare Inc. His research interests include applications of chaotic dynamical theory, combinatorial optimization, mobile networks, and ubiquitous computing. Hiroyuki Morikawa received his B.E., M.E., and D.E. in Electrical Engineering from the University of Tokyo in 1987, 1989, and 1992. He is currently an Associate Professor in the Department of Frontier Informatics at the University of Tokyo and is in charge of NICT's Mobile Networking Group. His research interests are in the areas of computer networks, mobile computing/networks, ubiquitous computing, and network services. He serves as Editor of Transactions of the IEICE and has been on the technical program committees of IEEE/ACM conferences and workshops. He sits on numerous telecommunications advisory committees and frequently serves as a consultant to the government.     

Multichannel frequency conversion experiment using fibre four-wave mixing

Multichannel frequency conversion is demonstrated using four-wave mixing. A polarisation independent configuration is employed, by which polarisation control for each signal is not necessary. By setting the pump light frequency at the zero-dispersion wavelength of the fibre, three FSK modulated signals with a frequency spacing of 70 GHz are simultaneously converted with an equal efficiency of -27.5 dB. Bit error rate measurements confirm the feasibility of this conversion scheme.<>     

Self‐Organized Nanoporous Anodic Titania Films and Ordered Titania Nanodots/Nanorods on Glass

We report a new method to fabricate self‐organized nanoporous titania films (pore diameter ≈ 30 nm; ≈ 1100 nm thick) and ordered titania nanorod arrays (rod diameter ≈ 30–60 nm; 70–260 nm high) by combined anodizing of superimposed Al/Ti layers sputter‐deposited on glass substrates. The titania nanostructures mimic the ordered nanoporous anodic alumina films via a through‐mask anodization. We propose a new anodizing electrolyte, i.e., a diluted nitric acid solution, for fabricating uniform, self‐organized, ordered nanoporous titania films with parallel cylindrical pores and without any thickness limit. More significantly, the nanoporous titania films contain a small amount of titanium nitride and dissociated nitrogen, and exhibit a moderate transparency and an enhanced absorption throughout the UV and visible light regions of the electromagnetic spectrum. After heating at 600 °C for 2 h, the nanoporous titania films develop a small absorption red‐shift and exhibit high photocatalytic activity under UV illumination.     

Optical pulse compression based on stationary rescaled pulse propagation in a comblike profiled fiber

In this paper, optical pulse compression using a comblike profiled fiber (CPF) is theoretically and experimentally studied, in which highly nonlinear fibers and single-mode fibers are alternately concatenated. Stationary rescaled pulse (SRP), is the main focus, which is a recently discovered nonlinear stationary pulse in CPF. The fundamental characteristics of SRP are investigated, and SRP propagation is applied to the design of the CPF pulse compressor. Using the proposed design method, the specifications of the CPF can easily be controlled, such as the compression ratio per step of the CPF or the pedestal of the output pulse. Two experimental results of pulse compression using the CPF based on the proposed design method are shown: 1) pulse compression with a large compression ratio per step of the CPF and 2) low-pedestal and wideband wavelength-tunable compression. A parametric noise-amplification phenomenon occurring in a compression process for an optical pulse sequence is also numerically analyzed.     

Numerical simulation of ultra-compact electro-optic modulator based on nanoscale plasmon metal gap waveguides

An ultra-compact Mach-Zehnder (MZ) electro-optic (EO) modulator composed of nanoscale metal gap waveguides is numerically demonstrated. Propagation of surface plasmon polaritons in nano-size channels and their EO modulations is investigated by the finite-difference time-domain method considering the Lorentz-Drude model. The half-wave voltage (V _pi) of the resulting MZ modulator for push-pull operation is 1.73 V using the interference arm with a sub-micron length (500-nm).     

A 1.3-GHz fifth-generation SPARC64 microprocessor

A fifth-generation SPARC64 processor is fabricated in 130-nm partially depleted silicon-on-insulator CMOS with eight layers of Cu metallization. At V/sub dd/ = 1.2 V and T/sub a/ = 25/spl deg/C, it runs at 1.3 GHz and dissipates 34.7 W. The chip contains 191 M transistors with 19 M logic circuits in an area of 18.14 mm /spl times/ 15.99 mm and is covered with 5858 bumps, of which 269 are for I/O signals. It is mounted in a 1360-pin land-grid-array package. The 16-byte-wide system bus operates with a 260-MHz clock in single-data-rate or double-data-rate modes. This processor implements an error-detection mechanism for execution units and data path logic circuits in addition to on-chip arrays to detect data corruption. Intermittent errors detected in execution units and data paths are recovered via instruction retry. A soft barrier clocking scheme allows amortization of the clock skew and jitter over multiple cycles and helps to achieve high clock frequency. Tunability of the clock timing makes timing closure easier. A relatively small amount of custom circuit design and the use of mostly static circuits contributes to achieve short development time.     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

Electrical Properties of Isotropic Conductive Adhesives Composed of Silicone-Based Elastomer Binders Containing Ag Particles

The electrical properties of isotropic conductive adhesives (ICAs) with two different types of silicone-based binder containing Ag particles were examined. The ICAs were printed on glass substrates in order to prepare specimens for evaluating the electrical properties. In the case of adhesives containing a denatured silicone binder, both the curing and cooling steps in the isothermal curing process generated electrical conductivity. Adhesives that were cured at 120°C to 200°C exhibited similar values of electrical resistivity regardless of the different curing temperatures. By contrast, electrical conductivity was generated only during the cooling step when adhesives containing a dimethyl methylvinyl siloxane were isothermally cured. In this case, adhesives cured above 160°C exhibited high electrical resistivity. In evaluating the temperature dependence of the electrical resistivity, we found physical annealing to have significantly different effects on these specimens. In addition, we were able to make small sensitive variations in the properties of silicone-based ICAs by controlling the isothermal annealing and thermal cycling processes.     

Implementation in Japan [ISDN]

INS-Net, Nippon Telegraph and Telephone's (NTT's) commercial integrated services digital network (ISDN) service, is described. There are two types of INS-Net service. INS-Net 64 provides basic rate interface service, and INS-Net 1500 provides primary rate interface service. The implementation of INS-Net and the promotion, application, and penetration of ISDN services are discussed. It is argued that as the number of useful applications grows, the number of subscribers will rise accordingly, particularly among business users. This increased volume of both applications and users will in turn lead to lower ISDN CPE costs, and will make ISDN an indispensable means to business activities in the 1990s     

CAD-compatible high-speed CMOS/SIMOX gate array using field-shieldisolation

A specific 0.5 μm CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV_ds) lowering. FS isolation is capable of improving BV_ds because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BV_ds was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 μm using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V