Automatic facial expression recognition: feature extraction and selection

In this paper, we investigate feature extraction and feature selection methods as well as classification methods for automatic facial expression recognition (FER) system. The FER system is fully automatic and consists of the following modules: face detection, facial detection, feature extraction, selection of optimal features, and classification. Face detection is based on AdaBoost algorithm and is followed by the extraction of frame with the maximum intensity of emotion using the inter-frame mutual information criterion. The selected frames are then processed to generate characteristic features using different methods including: Gabor filters, log Gabor filter, local binary pattern (LBP) operator, higher-order local autocorrelation (HLAC) and a recent proposed method called HLAC-like features (HLACLF). The most informative features are selected based on both wrapper and filter feature selection methods. Experiments on several facial expression databases show comparisons of different methods.     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Analysis of Asynchronous Band-Limited DS-CDMA with MMSE Multiuser Detector over Generalized-<Emphasis Type="Italic">k</Emphasis> Fading Channels

In this paper, we investigate bit-error-rate (BER) performance of a minimum mean-squared error (MMSE) multiuser receiver for asynchronous band-limited direct- sequence code-division multiple-access (DS-CDMA) systems. We focus on the BER performance in the presence of multitone jamming (MTJ) over frequency-selective multipath fading channels. We consider the generalized-K fading model in our analysis, as it can model a large spectrum of fading-channel characteristics. We also analyze the effects of band- limited pulse shape on the BER performance of the system. Multipath diversity based on the maximal-ratio combining (MRC) scheme is employed to combat fading effects. Our analytical expressions are valid for arbitrary diversity levels and fading parameters. Spectrum raised cosine (SRC) and Beaulieu–Tan–Damen (BTD) pulse shapes are employed for numerical analysis. Numerical results show that in the presence of MTJ and under various channel conditions, the MMSE based receiver gives better BER performance than the one without it. Moreover, the system with BTD pulses outperforms the one with SRC pulses.     

Power efficiency enhancement analysis of an inverse class D power amplifier for NB-IoT applications

Analog Integrated Circuits and Signal Processing - The power amplifiers (PAs) are generally the most power-consuming building blocks in Radio Frequency (RF) transceivers. This paper presents a high...     

A Comparison of ZnO Nanowires and Nanorods Grown Using MOCVD and Hydrothermal Processes

A comparison of ZnO nanowires (NWs) and nanorods (NRs) grown using metalorganic chemical vapor deposition (MOCVD) and hydrothermal synthesis, respectively, on p-Si (100), GaN/sapphire, and SiO₂ substrates is reported. Scanning electron microscopy (SEM) images reveal that ZnO NWs grown using MOCVD had diameters varying from 20 nm to 150 nm and approximate lengths ranging from 0.7 μm to 2 μm. The NWs exhibited clean termination/tips in the absence of any secondary nucleation. The NRs grown using the hydrothermal method had diameters varying between 200 nm and 350 nm with approximate lengths between 0.7 μm and 1 μm. However, the NRs grown on p-Si overlapped with each other and showed secondary nucleation. x-Ray diffraction (XRD) of (0002)-oriented ZnO NWs grown on GaN using MOCVD demonstrated a full-width at half-maximum (FWHM) of 0.0498 (θ) compared with 0.052 (θ) for ZnO NRs grown on similar substrates using hydrothermal synthesis, showing better crystal quality. Similar crystal quality was observed for NWs grown on p-Si and SiO₂ substrates. Photoluminescence (PL) of the NWs grown on p-Si and SiO₂ showed a single absorption peak attributed to exciton–exciton recombination. ZnO NWs grown on GaN/sapphire had defects associated with oxygen interstitials and oxygen vacancies.     

MFLP: a low power encoding for on chip networks

Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approach assigns the symbols to data word in such a way that the more frequent words are sent by less power consumption. This algorithm dedicates the symbols with less ones to high probability data and uses transition signaling to transmit data. The proposed method, unlike the existing low power encoding, does not rely on spatial redundancy and keeps the width of the bus constant. Experimental evaluations show that our approach reduces the power dissipation up to 46 % with 2.70, 0.51, and 15.43 % power, critical path and area overhead in the NoCs, respectively.