A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS

This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occupies 0.09 mm/sup 2/ and consumes 21 mW.     

The effects of hypercapnia on early and later phases of phrenic neurogram during early maturation

In this paper, we investigate the influence of hypercapnia on the early and late phases of the phrenic neurogram using the matching pursuit (MP) method in the decebrated piglets. The phrenic neurogram was recorded from 8 piglets (4-7 days old) during control (40% O2 with 5% end-tidal CO2), the mild hypercapnia (40% O2 with 7% end-tidal CO2), and the severe hypercapnia (40% O2 with 15% end-tidal CO2). The time-frequency representations, atoms, of the phrenic neurogram are calculated from the 5 consecutive phrenic neurogram burst for each piglet for each condition using the MP method after vagotomy and chemodenervation. Our results show that the energy percentage of atoms representing the nonperiodic neural activities (NPNAs) significantly increased when the CO2 concentration was shifted from 7% to 15% in the early phase (the first half) of the phrenic neurogram. In addition, the energy percentage of atoms representing the periodic neural activities (PNAs) decreased in the late phase (the second half) when the CO2 concentration was shifted from 7% to 15% (p < 0.01). As a summary, our result suggest that hypercapnia results in significant changes in the phrenic neurogram, an output of the respiratory neural networks in the medulla, both in time and frequency domians during early maturation.     

Scheme for reducing size of coefficient memory in FFT processor

Long fast Fourier transforms (FFTs) are required in applications such as orthogonal frequency division multiplexing, radars and sonars. It is highly desirable to reduce the size and power requirements of the FFT so as to realise single chip long FFT-based systems targeting portable applications. Presented here is a novel technique to reduce the coefficient memory almost by a factor of four by exploiting the relationships among the coefficient values thereby significantly reducing the area and power requirements of the hardware     

Neural Network Based Receiver for Multiuser Detection in MC-CDMA Systems

In this paper, we present a multiuser detection technique based on artificial neural network (NN) for synchronous multicarrier code division multiple access systems over Rayleigh fading channels. To test the robustness of the proposed receiver, also the effect of power control problem is studied with a comparative manner. Bit error rate (BER) performance of the NN based receiver is compared with the single user bound and conventional receivers. Although the BER performance of the conventional receiver degrades as the number of the users and power level differences among the users increase, as a decision structure, neural network based receiver gives closer BER performance to the single user bound.     

Design of practical broadband matching networks with commensurate transmission lines

To design broadband matching networks for microwave communication systems, commercially available computer aided design (CAD) tools are always preferred. But these tools need proper matching network topology and element values. Therefore, in this paper, a practical method is proposed to generate distributed-element matching networks with good initial element values. Then, the gain performance of the designed matching network can be optimized employing these tools. The utilization of the proposed method is illustrated by means of the given example. It is shown that proposed method provides very good initials for CAD tools.     

Analysis and Implementation of Multiple–Input, Multiple–Output VBLAST Receiver From Area and Power Efficiency Perspective

This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless system from the hardware implementation perspective and identifies those processing elements that consume more area and power due to complex signal processing. This paper models a scalable VBLAST receiver based on minimum mean square error (MMSE) nulling criteria assuming a block flat fading channel. After identifying the major area and power consuming blocks, this paper proposes two area and power efficient VLSI architectures for the block that computes pseudoinverse of the channel matrix. This paper discusses different tradeoff issues in both architectures and compares them with the architectures in the literature     

A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z?, good linearity and excellent output–input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.