Enhanced fair earliest due date first scheduling strategy for multimedia applications in LTE downlink framework

Guaranteeing a certain delay threshold for delay‐sensitive applications in long term evolution (LTE) cellular communication system is a very challenging mission. By implementing an optimal scheduling strategy, this mission will be achieved. In this article, a novel scheduler is introduced in order to meet a predefined level of service quality by guaranteeing a specific delay threshold for delay‐sensitive applications in LTE cellular systems. The proposed scheduler assigns the available resource blocks (RBs) to active user equipments (UEs) tacking into consideration several attributes. The expiration date of each packet, the channel quality, the average data rate previously achieved by each UE, and the number of dropped packets for each UE compared with the average number of packets totally dropped are all considered in the proposed scheduler working mechanism. Consequently, the proposed scheduling strategy reduces the number of packets dropped for multimedia applications, and at the same time maximizes the overall throughput of the network. Simulation results are provided to study and evaluate the performance of the proposed scheduling strategy. A comparative study is presented between the proposed strategy and the most recent scheduling techniques. The obtained results prove that the proposed scheduling strategy has considerably acceptable and appreciated results compared with the results of the state‐of‐the‐art scheduling techniques.     

A translinear principle based low-power high-precision RMS-to-DC converter in CMOS technology

Analog Integrated Circuits and Signal Processing - In the present study, a low-power high-precision current-mode CMOS true root mean square (RMS)-to-DC converter is presented based on the...     

Fabrication of porous ZnO via electrochemical etching using 10 wt% potassium hydroxide solution

We described the fabrication of porous ZnO using the electrochemical etching method. ZnO thin films deposited by radiofrequency sputtering were etched electrochemically using 10 wt% KOH solution as an etching medium to obtain porous ZnO surface structure. A constant voltage of 15 V was applied to enhance the etching process. The etched samples were then characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), and photoluminescence (PL) spectroscopy to examine their structural and optical properties. XRD spectra showed that by performing the electrochemical etching process, porous ZnO could be obtained without severely deteriorating the crystallinity of the samples. Moreover, SEM characterization revealed that hillock-type porous ZnO was fabricated successfully. In addition, the cross-sectional SEM images revealed that there were only minimal changes in the layer thickness after the ZnO had been etched for various lengths of time. This finding shows the dominance of the vertical etching process. Notably, the intensity of PL spectra increased and the PL excitation peak exhibited a red shift trend as the etching time increased. These observations are due to the increase of the surface to volume ratio of the ZnO surface and the strain relaxation along the dislocation and grain boundary.     

Error Performance of DQPSK with EGC Diversity Reception over Fading Channels

This paper derives the average bit error probability (BEP) of differential quaternary phase shift keying (DQPSK) with postdetection equal gain combining (EGC) diversity reception over independent and arbitrarily correlated fading channels. First, using the associated Legendre functions, the average BEP of DQPSK is analyzed over independent Rayleigh, Nakagami-m, and Rician fading channels. Finite-series closed-form expressions for the average BEP of DQPSK over L-branch independent Rayleigh and Nakagami-m fading channels (for integer Lm) are presented. Besides, a finite-series closed-form expression is given for the average BEP of differential binary phase shift keying (DBPSK) with EGC over independent Rician fading channels. Second, an alternative approach is propounded to study the performance of DQPSK over arbitrarily correlated Nakagami-m and Rician fading channels. Relatively simple BEP expressions in terms of a finite sum of a finite-range integral are proposed. Moreover, the penalty in signal to noise ratio (SNR) due to arbitrarily correlated channel fading is also investigated. Finally, the accuracy of the results is verified by computer simulation.     

New evolution in two-way relay networks based on physical layer network coding

Telecommunication Systems - In this paper, a physical-layer network coding (PNC) method is offered for a two-way relay network with spatial modulation (SM) for source node and relay node. For this...     

Data broadcasting strategies for cognitive radio based AMI networks

Wireless Networks - Communication systems play an important role in smart grid (SG). Advanced Metering Infrastructure (AMI) is hybrid architecture in smart grid comprising of smart meters and...     

High-voltage DMOS integrated circuits using floating-gate protection technique

An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 μm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.     

A universal low-noise analog receiver baseband in 65-nm CMOS

In this paper, a novel universal receiver baseband approach is introduced. The chain includes a post-mixer noise shaping blocker pre-filter, a programmable-gain post mixer amplifier (PMA) with blocker suppression, a differential ramp-based novel linear-in-dB variable gain amplifier and a Sallen–Key output buffer. The 1.2-V chain is implemented in a 65-nm CMOS process, occupying a die area of 0.45 mm². The total power consumption of the baseband chain is 11.5 mW. The device can be tuned across a bandwidth of 700-KHz to 5.2-MHz with 20 kHz resolution and is tested for two distinct mobile-TV applications; integrated services digital broadcasting-terrestrial ISDB-T (3-segment f _c = 700 kHz) and digital video broadcasting-terrestrial/handheld (DVB-T/H f _c = 3.8 MHz). The measured IIP3 of the whole chain for the adjacent blocker channel is 24.2 and 24 dBm for the ISDB-T and DVB-T/H modes, respectively. The measured input-referred noise density is 10.5 nV/sqrtHz in DVB-T/H mode and 14.5 nV/sqrtHz in ISDB-T mode.     

Body controlled threshold voltage shifting variable gain current mirror

A programmable high-speed source-series-terminated driver with signal boost capability is presented. The driver uses only one main input data tap and is divided into main units and auxiliary units. A passive high pass filter is utilized to detect data transitions and control the inputs of the auxiliary units to enable a programmable amplitude boost for the output signal. The corner frequency of the high pass filter is adjusted depending on the data rate. Further, the amount of the high frequency signal boost can be adjusted depending on the loss of the channel. HSPICE simulations are used to demonstrate the performance of the driver at 10, 20 and 40 Gbps data rates. At 40 Gbps, the driver is capable of equalizing a PRBS9 data pattern signal through a channel that has a loss of 9 dB. At worst case conditions and 40 Gbps date rate, the driver achieves a differential eye-opening amplitude of 201 mVppd and an eye-opening of 0.952 UI. The driver is designed using 28 nm CMOS process and uses a nominal 1 V supply voltage. It consumes a maximum of 12 mW of at-speed power.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.