A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).     

TD-LTE:抢占无线全新商机带动全球发展势态

LTE是目前大部分电信运营商首选的下一代移动通信技术,已有100多家运营商承诺将于2010年开始部署LTE.不过,在非成对频段部署LTE的商机却常被忽略.     

Multicarrier constant envelope OFDM signal design for radar applications

Orthogonal frequency division multiplexing (OFDM) radar signals have been introduced for high range resolution radars. These signals have prominent properties such as favorable ambiguity function, high bandwidth efficiency, and possibility of use in dual mode radar/communication systems. But the large amplitude fluctuations of the OFDM signal make it susceptible to system nonlinearities. To alleviate this problem, constant envelope OFDM (CE-OFDM) signal has been introduced which combines orthogonal frequency division multiplexing and phase modulation or frequency modulation. Although several works have been reported on OFDM radar signal design, there is no a systematic approach for designing CE-OFDM signals for radar applications. In this paper we will focus on CE-OFDM signal design for radar applications. Two different methods for designing a CE-OFDM signal with favorable ambiguity functions are introduced. The first one is based on modulating a complementary set of sequences on different sub-carriers while the second is based on using a proper single carrier coded signal and then extracting its most similar multicarrier OFDM or CE-OFDM coded signal.     

A theoretical discussion on the foundation of Stone??s blind source separation

This paper discusses the theoretical foundation of Stone’s BSS (Stone in Neural Comput 13:1559–1574, 2001; Stone in Independent Component Analysis: A Tutorial Introduction, A Bradford Book, London, 2004), and it proposes a novel BSS approach based on second-order statistics of the responses of two different linear filters to source signals. The proposed approach which includes Stone’s BSS as a special case helps us to understand how generalized eigenvalue decomposition (GEVD) concludes separating vectors in Stone’s BSS. It obtains the separating vectors by simultaneous diagonalization of covariance matrices of two different linear filters responses to the mixtures. The two employed linear filters are selected dependent on source signals structures under the assumption that they have different responses to source signals. Here, two FIR filters with coefficients selected in an opposite probabilistic way have been suggested for the proposed BSS. The proposed BSS method has been compared with Stone’s BSS, SOBI and AMUSE over speech and image mixtures in different noise levels.     

A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.     

Motion-compensated DCT temporal filters for efficient spatio-temporal scalable video coding

Although most of the proposals for implementing motion-compensated temporal filtering (MCTF) schemes are based on the wavelet transform, in this paper, we propose an MCTF framework based on the discrete cosine transform (DCT). Using DCT decimation and interpolation, several temporal decomposition structures named motion-compensated DCT temporal filters (MCDCT-TF) are introduced. These structures are able to employ filters of any length with particular emphasis on 5/3 DCT and 7/4 DCT. The proposed MCDCT-TF and the two-dimensional (2D) DCT decimation technique are incorporated into H.264/AVC to provide spatio-temporal scalability. Compared with the current MCTF-based lifting schemes such as Haar, and 5/3 wavelet filters, simulation results show that the proposed MCDCT-TF utilizing longer tap DCT filters achieves a significant improvement in coding gain. The impact of odd/even group of frames, the decimation/interpolation ratios, and motion-compensated connectivity on the MCDCT-TF performance are also analyzed. Moreover, simulation results show that the performance of the presented scalable video coding is close to the single layer H.264/AVC and is slightly inferior to the temporal scalability supported in JSVM, the state-of-the-art scalable video coding standard, that gets its gain from Hierarchical B-pictures. However, our spatio-temporal coding scheme outperforms the spatio-temporal supported in JSVM even if it uses hierarchical B-pictures to improve its gain.     

Targeted Delivery of Anesthetic Agents to Bone Tissues using Conductive Microneedles Enhanced Iontophoresis for Painless Dental Anesthesia

Pain management during dental procedures is a cornerstone for successful daily practice. In current practice, the traditional needle and syringe injection is used to administer local anesthesia. However, the appearance of long needles and the pain associated with it often leads to dental anxiety deterring timely interventions. Microneedles (MNs) have emerged as a minimally invasive alternative to hypodermic needles and shown to be effective in transdermal drug delivery applications. In this article, the potential use of MNs for local anesthesia delivery in dentistry is explored. The development of a novel conductive MN array that can be used in combination with iontophoresis technique to achieve drug penetration through the oral mucosa and the underlying bone tissue is presented. The conductive MN array plays a dual-role, creating micro-conduits and lowering the resistance of the oral mucosa. The reduced tissue resistance further enhances the application of a low-voltage current that is able to direct and accelerate the drug molecules to target the sensory nerves supplying teeth. The successful delivery of lidocaine using this new strategy in a clinically relevant rabbit incisor model is shown to be as effective as the current gold standard.     

All two-input logic gates by a single-stage single electron box

In this paper, the design of all two-input logic gates is presented by only a single-stage single electron box (SEB) for the first time. All gates are constructed based on a same circuit. We have used unique periodic characteristics of SEB to design these gates and present all two-input logic gates (monotonic/non-monotonic, symmetric/non-symmetric) by a single-stage design. In conventional monotonic devices, such as MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible by only a single-stage design, and a multistage design is required which leads to more complexity, higher power consumption and less speed of the gates. We present qualitative design at first and then detailed designs are investigated and optimised by using our previous works. All designs are verified by a single electron simulator which shows correct operation of the gates.     

Underlay Device to Device Communication with Imperfect Interference Channel Knowledge

The objective of any night vision system is to enable a person to see in the dark. A low-contrast image puts a contrast constraint on the human observer visibility at night. This is the basic reason for the large number of accidents at night. This research presents two proposed approaches to enhance the visibility of the infrared (IR) night vision images through an efficient histogram processing. The first approach is based on contrast limited adaptive histogram equalization. The second proposed approach depends on histogram matching. The histogram matching uses a reference visual image for converting night vision images into good quality images. The obtained results are evaluated with quality metrics such as entropy, average gradient, contrast improvement factor and sobel edge magnitude.     

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults

Testing for small-delay defects (SDDs) has become necessary as technology further scales. Existing tools and methodologies for generating SDD patterns suffer from: limited long-paths sensitization capability, overwhelming pattern volume, time-consuming pattern generation process, and vague evaluations of pattern quality. Such situation places patterns in a dilemma where the generation and application effort are huge yet the results cannot reflect the physical phenomena clearly enough for correct binning and diagnosis. In this paper, we focus on establishing a pattern generation flow that produces patterns of high application value. Firstly, critical faults are identified in order to generate high-quality original pattern repository with n-detect ATPG.A novelpattern evaluation and selection method that further minimizes pattern count while maintaining the SDD detection ability is then presented. Top-off ATPG is then performed to ensure meeting the target fault coverage. Along with the flow, multiple evaluation metrics are also proposed to measure the pattern’s efficiency on SDD coverage, unique SDD detection, detectable SDD size, long path distribution, etc. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5× without impairing its average delay and saves approximately 80 % CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, the generated pattern set detects equivalent or even more SDDs with significantly reduced pattern count.