Dynamic stiffness elements and their applications for plates using first order shear deformation theory

Dynamic stiffness elements for plates are developed using first order shear deformation theory to carry out exact free vibration analysis of plate assemblies. The analysis has been facilitated by the application of Hamiltonian mechanics and symbolic computation. The Wittrick–Williams algorithm has been used as the solution technique. Results have been extensively validated using published literature for both uniform and non-uniform plates. Some finite element results are also provided. The accuracy and computational efficiency of the method are demonstrated. In the final part of the investigation, significant plate parameters are varied and their subsequent effects on the free vibration characteristics are studied.     

Simulation of single phase non-Newtonian flow characteristics of heavy crude oil through horizontal pipelines

The effect of diameter, velocity, and temperature on flow properties of heavy crude oil in three horizontal pipelines using computational fluid dynamics (CFD) was studied. The flow characteristics were simulated by using CFD software, ANSYS Fluent 6.2. The mesh geometry of the pipelines having inner diameter of 1, 1.5, and 2 inch were created by using Gambit 2.4.6. From grid independent study, 221, 365 mesh sizes were selected for simulation. The CFD ANSYS Fluent 6.2 Solver predicted the flow phenomena, pressure, pressure drop, wall shear stress, shear strain rate, and friction factor. A good agreement between experimental and CFD simulated values was obtained.     

Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18 μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01 pV s. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33 LSB and a differential nonlinearity (DNL) of 0.14 LSB. The DAC can achieve a maximum measured SFDR of 65.19 dB for 97.50 kHz signal at a sampling rate of 100 MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07 MHz signal the measured SFDR is 56.84 dB at 100 MSPS sampling rate. At 50 MSPS sampling frequency and 146 kHz signal the SFDR of the DAC is 65.90 dB. The measured SFDR at 538 kHz signal is 63.62 dB for a sampling rate of 50 MSPS. Measured third order intermodulation distortion of the DAC is 58.55 dB, for a dual tone test with 1.03 MHz and 1.51 MHz signals at 50 MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06 MHz signal and 100 MSPS sampling frequency, the power dissipation of the DAC is 20.74 mW with 1.8 V supply.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

A universal ion implantation model for all species intosingle-crystal silicon

A physically based model for ion implantation of any species into single crystal silicon has been developed, tested and implemented in the ion implant simulator, UT-MARLOWE. In this model, an interpolation scheme, based on mathematical properties of ion-target interatomic potential, was employed and implemented to calculate the scattering process. Using this scheme, the resulting energy, direction and momentum of the ion and target can be derived from the existing scattering tables of UT-MARLOWE without calculating the entire scattering process. The method has advantages in terms of both accuracy and computational efficiency, as well as significantly reduced cost of code development. The impurity profiles and damage profiles predicted by the model simulations have been compared with secondary ion mass spectroscopy (SIMS) and Rutherford backscattering spectrometry (RBS), and excellent agreement with experimental data has been achieved     

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Based on the energy-dispersion relation in each region of the gate-dielectric-silicon system, a tunneling model is developed to understand the gate current as a function of voltage and temperature. The gate capacitance is self-consistently calculated from Schrodinger and Poisson equations subject to the Fermi-Dirac statistics, using the same band structure in the silicon as used for tunneling injection. Franz two-band dispersion is assumed in the dielectric bandgap. Using a Wentzel-Kramer-Brillouin (WKB)-based approach, direct and Fowler-Nordheim (FN) tunneling and thermionic emission are considered simultaneously. The model is implemented for both the silicon conduction and valence bands and both gate- and substrate-injected currents. ZrO/sub 2/ NMOSFETs were studied through temperature-dependent C/sub g/-V/sub g/ and I/sub g/-V, simulations. The extracted band gaps and band offsets of the ZrO/sub 2/- and interfacial-Zr-silicate-layer are found to be comparable with the reported values. The gate currents in ZrO/sub 2/-NMOSCAPs are found to be primarily contributed from the silicon conduction band and tunneling appears to be the most probable primary mechanism through the dielectric. Oscillations of gate currents and kinks of gate capacitance were observed near the flat-band in the experiments. These phenomena might be caused by the interface states.     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

Active filter system implementation

Adjustable speed AC drives with low input current THD are becoming increasingly important in industry. This article has detailed the implementation of a parallel active filter, which is integrated within a 450 kW adjustable speed drive to provide an overall system which conforms to IEEE 519, and which provides significant benefits on a system level. The design of the active filter is seen to be driven by overall system specifications which include input current THD, efficiency, displacement power factor, a high level of integration with the load converter, and cost targets. Active filter operation and control has been analyzed at a detailed level, and fundamental issues relating to current regulator topology and operation, limits on compensation capability, DC bus control, switching frequency ripple suppression, etc., have all been addressed, and have all been shown to be very important in terms of helping the system meet its performance objectives. The overall drive system including the active filter, meets IEEE 519 by reducing the supply current THD from 26.8% without the active filter to 4.1% with the active filter operating. This is achieved in presence of supply voltage THD of 2.3% and filter terminal voltage V _f unbalance of 1.3% and, includes an ASD load induced subharmonic component at 33 Hz. Further, individual harmonic limits are met up to the 35th harmonic     

Some principles for designing a wide-area WDM optical network

We explore design principles for next-generation optical wide-area networks, employing wavelength-division multiplexing (WDM) and targeted to nationwide coverage. This optical network exploits wavelength multiplexers and optical switches in routing nodes, so that an arbitrary virtual topology may be embedded on a given physical fiber network. The virtual topology, which is used as a packet-switched network and which consists of a set of all-optical “lightpaths”, is set up to exploit the relative strengths of both optics and electronics-viz. packets of information are carried by the virtual topology “as far as possible” in the optical domain, but packet forwarding from lightpath to lightpath is performed via electronic switching, whenever required. We formulate the virtual topology design problem as an optimization problem with one of two possible objective functions: (1) for a given traffic matrix, minimize the network-wide average packet delay (corresponding to a solution for present traffic demands), or (2) maximize the scale factor by which the traffic matrix can be scaled up (to provide the maximum capacity upgrade for future traffic demands). Since simpler versions of this problem have been shown to be NP-hard, we resort to heuristic approaches. Specifically, we employ an iterative approach which combines “simulated annealing” (to search for a good virtual topology) and “flow deviation” (to optimally route the traffic-and possibly bifurcate its components-on the virtual topology). We do not consider the number of available wavelengths to be a constraint, i.e., we ignore the routing of lightpaths and wavelength assignment for these lightpaths. We illustrate our approaches by employing experimental traffic statistics collected from NSFNET