Industrie 4.0 Readiness: Green Computing in Relation with Key Performance Indicator for a Manufacturing Industry

Mobile Networks and Applications - An effective measure of Key Performance Indicators (KPIs) is of great significance to enhance the capabilities of a decision support system (DSS) of any...     

Speed, power, area, and latency tradeoffs in adaptive FIR filteringfor PRML read channels

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed and latency remain as the main performance criteria for the target application. The proposed parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed, and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18-μm L-effective CMOS technology and operates at 550 MSamples/s. Trading off filter latency to improve speed is also discussed     

Extended Virtual Boundary and Its Application in Dynamic Spectrum Allocation

This paper presents an efficient dynamic spectrum allocation （DSA） scheme in a flexible spectrum licensing environment where multiple networks coexist and interfere with each other. In particular, an extension of virtual boundary concept in DSA is proposed, which is spectrally efficient than the previous virtual boundary concept applied to donor systems only. Here, the same technique is applied to both donor and rental systems so as to further reduce the occurrences where the insertion of guard bands is obligatory and as a result provides better spectral efficiency. The proposed extension improves the spectrum utilization without any compromise on interference and fairness issues.     

A load-aware energy-efficient and throughput-maximized asynchronous duty cycle MAC for wireless sensor networks

Being a pivotal resource, conservation of energy has been considered as the most striking issue in the wireless sensor network research. Several works have been performed in the last years to devise duty cycle based MAC protocols which optimize energy conservation emphasizing low traffic load scenario. In contrast, considering the high traffic situation, another research trend has been continuing to optimize both energy efficiency and channel utilization employing rate and congestion control at the MAC layer. In this paper, we propose A Load-aware Energy-efficient and Throughput-maximized Asynchronous Duty Cycle MAC (LET-MAC) protocol for wireless sensor networks to provide an integrated solution at the MAC layer considering both the low-and high-traffic scenario. Through extensive simulation using ns-2, we have evaluated the performance of LET-MAC. LET-MAC achieves significant energy conservation during low traffic load (i.e., no event), compared to the prior asynchronous protocol, RI-MAC, as well as attains optimal throughput through maximizing the channel utilization and maintains lower delay in regard to the CSMA/CA-like protocol during a high volume of traffic (i.e., when an event occurs).     

Bio-cellular processes modeling on silicon substrate: receptor–ligand binding and Michaelis Menten reaction

Reducing transmit power is the most straightforward way towards more energy-efficient communications, but it results in lower SNRs at the receiver which can add a performance and/or complexity cost. At low SNRs, synchronization and channel estimation errors erode much of the gains achieved through powerful turbo and LDPC codes. Further expanding the turbo concept through an iterative receiver—which brings synchronization and equalization modules inside the loop—can help, but this solution is prohibitively complex and it is not clear what can and what cannot be a part of the iterative structure. This paper fills two important gaps in this field: (1) as compared to previous research which either focuses on a subset of the problem assuming perfect remaining parameters or is computationally too complex, we propose a proper partitioning of algorithm blocks in the iterative receiver for manageable delay and complexity, and (2) to the best of our knowledge, this is the first physical demonstration of an iterative receiver based on experimental radio hardware. We have found that for such a receiver to work, (1) iterative timing synchronization is impractical, iterative carrier synchronization can be avoided by using our proposed approach, while iterative channel estimation is essential, and (2) the SNR gains claimed in previous publications are validated in indoor channels. Finally, we propose a heuristic algorithm for simplifying the carrier phase synchronization in an iterative receiver such that computations of the log likelihood ratios of the parity bits can be avoided to strike a tradeoff between complexity and performance.     

Special Issue: Technological Advancements in Wireless and Optical Communication Systems

Wireless Personal Communications -     

SER and throughput analysis of space–time analog network coded relaying system over shadowed Rician fading channels

Wireless Networks - This research article presents an innovative approach based on analog network coding (ANC) in conjunction with space time block coding (STBC) which is termed as space time...     

New two CFOA-based sinusoidal RC oscillators with buffered outlet

Using a unified representation for a class of buffered-outlet two current-feedback operational amplifier (CFOAs)-based sinusoidal oscillators, new circuits of this type can be systematically discovered. A catalogue of four circuit structures, each structure realizing nine oscillator circuits, is presented. Moreover, using the RC:CR transformation, additional nine oscillator circuits can be obtained from each structure. While each circuit requires five passive elements, some of the circuits enjoy one or more of the following attractive features: use of grounded capacitors, feasibility of absorbing the parasitic components of the CFOAs and orthogonal tuning of the frequency and the startup condition of oscillation.     

A novel approach to high-level switching activity modeling withapplications to low-power DSP system synthesis

We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 × 16 bit array multiplier implemented in a 0.6-μ process with 3.3 V supply voltage     

Large signal analysis of mixers with difference frequency injection

Large signal analysis of mixers excited by three tone signals is presented. The special case of two equal-amplitude sinusoids plus a difference-frequency injection is considered in detail and the results are compared, whenever possible, with previously published results. Contrary to previously published results, it is shown that even under large signal conditions and strong nonlinearity it is possible, at least in theory, to totally eliminate the third-order intermodulation when the amplitudes of the equal-amplitudes input sinusoids and the difference-frequency injection are equal.