A signaling architecture for wireless ATM access networks

A multiservice wireless Asynchronous Transfer Mode (ATM) access system is considered from a signaling protocol viewpoint. In an attempt to generalize and extend results and experiences obtained from the specification, design, and implementation of fixed ATM‐based access networks, we extend the concept of the broadband V interface (referred to as VB) for application to wireless ATM access networks. The proposed architecture follows the signaling structure of Broadband ISDN (B‐ISDN) User–Network Interface (UNI), thus offering the possibility for integration of the wireless ATM access system into fixed B‐ISDN. It is shown that the use of the proposed access signaling architecture provides cost effective implementations without degrading the agreed Quality of Service (QoS), and simplifies call/connection and handover control. The evaluation of the proposed access signaling protocol structure yields results that fall within acceptable ATM signaling performance measures. A performance comparison of our approach with an alternative access signaling configuration is also carried out to quantify the relative gains. This revised version was published online in August 2006 with corrections to the Cover Date.     

An ultra low die area 8-b ADC and its generic calibration logic

The 8-bit voltage mode subrange A/D converter described in this paper operates in a mid-input signal frequency range of up to 20 MHz and requires at least an order of magnitude lower die area (0.06 mm²) than other A/D converters with a similar resolution. Moreover, it dissipates only 4.5 mW power and is supported by a calibration logic that is general enough to be used by several other measurement and instrumentation applications that require a real time adjustment of the amplitude and the level of their differential signals. This voltage mode subrange A/D converter architecture is actually an asynchronous two-step A/D converter that is based on a novel integer division operation. The current mode implementation of such an integer divider has already been employed by the authors in an innovative low area/power binary tree A/D conversion architecture. The voltage mode implementation of the integer divider allows the realization of the higher speed and lower power/area subrange A/D converter that is presented in this article.     

On the support of voice call continuity across UMTS and wireless LANs

In this paper, we address the architecture and the procedures that can enable voice call handover from UMTS to WLAN and we also study how efficiently the WLAN can support the voice calls transferred from UMTS. Our study is based on a practical simulation model that lets us quantify the maximum number of voice calls that can be handed over from UMTS to WLAN, subject to maintaining the same level of UMTS QoS and respecting some WLAN policies. In addition, several other voice call performance metrics are derived. Our results indicate that an IEEE 802.11e access point can support a limited number of voice calls handed over from UMTS, which depends primarily on the applied WLAN bandwidth sharing policy (i.e., how the bandwidth is shared between WLAN voice and data users) and the QoS requirements. The performance of the WLAN scheduling algorithm is also of paramount importance and in our study we consider the so‐called ARROW scheduler. Although the simulation results are derived for a specific bandwidth sharing policy, they can readily be scaled and provide practical upper bounds for the number of UMTS voice calls that can be seamlessly admitted to a WLAN access point. Copyright © 2007 John Wiley & Sons, Ltd.     

Comments on “Average LCR and AFD for SC diversity over correlated Weibull fading channels”

In a recent paper, two formulae for the average level crossing rate and fade duration at the output of dual-branch selection diversity receivers have been derived. In this short communication, some previously published works including results being in a more general setting are reviewed and compared.     

Side-information-dependent correlation channel estimation in hash-based distributed video coding

In the context of low-cost video encoding, distributed video coding (DVC) has recently emerged as a potential candidate for uplink-oriented applications. This paper builds on a concept of correlation channel (CC) modeling, which expresses the correlation noise as being statistically dependent on the side information (SI). Compared with classical side-information-independent (SII) noise modeling adopted in current DVC solutions, it is theoretically proven that side-information-dependent (SID) modeling improves the Wyner-Ziv coding performance. Anchored in this finding, this paper proposes a novel algorithm for online estimation of the SID CC parameters based on already decoded information. The proposed algorithm enables bit-plane-by-bit-plane successive refinement of the channel estimation leading to progressively improved accuracy. Additionally, the proposed algorithm is included in a novel DVC architecture that employs a competitive hash-based motion estimation technique to generate high-quality SI at the decoder. Experimental results corroborate our theoretical gains and validate the accuracy of the channel estimation algorithm. The performance assessment of the proposed architecture shows remarkable and consistent coding gains over a germane group of state-of-the-art distributed and standard video codecs, even under strenuous conditions, i.e., large groups of pictures and highly irregular motion content.     

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ADC that requires a light calibration logic (area: 0.123 mm², power: 72 mW) or a faster, tinier and even lower power ADC (area: 0.21 mm², power: 25 mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225 MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420 MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7 dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.     

Enabling technologies for the ‘always best connected’ concept

‘Always Best Connected’ (ABC) is considered one of the main requirements for next generation networks. The ABC concept allows a person to have access to applications using the devices and network technologies that best suits his or her needs or profile at any time. Clearly, this requires the combination of a set of existing and new technologies, at all levels of the protocol stack, into one integrated system. In this paper, a considerable set of the technologies, that are expected to play a key role towards the ABC vision, are presented. Starting from a reference architecture, the paper describes the required enhancements at certain levels of a traditional protocol stack, as well as technologies for mobility and end‐to‐end Quality of Service (QoS) support. The paper concludes with a case study that reveals the advantages of the ABC concept. This article replaces a previously published version (Wireless Communications and Mobile Computing; 5 (2): 175‐191. [DOI: 10.1002/wcm.207]). Retraction notice DOI: 10.1002/wcm.426 . Copyright © 2006 John Wiley & Sons, Ltd.     

Date movement and control substrate for parallel adaptive applications

In this paper, we present the Data Movement and Control Substrate (DMCS), a library which implements low‐latency one‐sided communication primitives for use in parallel adaptive and irregular applications. DMCS is built on top of low‐level, vendor‐specific communication subsystems such as LAPI (Low‐level Application Programme Interface) for IBM SP machines, as well as on widely available message‐passing libraries like MPI for clusters of workstations and PCs. DMCS adds a small overhead to the communication operations provided by the lower communication system. In return, DMCS provides a flexible and easy to understand application program interface for one‐sided communication operations. Furthermore, DMCS is designed so that it can be easily ported and maintained by non‐experts. Copyright © 2002 John Wiley & Sons, Ltd.