Practical Analog Circuit Diagnosis Based on Fault Features with Minimum Ambiguities

As numerous faults exist in practical analog circuits, new challenges arise in the field of diagnosis with large-scale target faults as well as fault features. To address this issue, firstly, an ambiguity model is built to measure the distinguishability between two faults. Then, the optimal fault features are obtained by analyzing the response curves of the circuit under test (CUT) to minimize the ambiguities among the faults. Finally, comparisons are made among three classification methods, including the maximum likelihood classifier (MLC), artificial neural networks (ANNs) and support vector machine (SVM), to demonstrate their own diagnostic abilities for practical use. Two examples are illustrated, and taking advantage of an automated implementation framework, 92 faults in total are examined in the second example. The experimental results show that good diagnostic performances can be obtained with the proposed method. However, when a practical case is encountered, the ANNs method may fail due to its high time and space complexity, while the MLC and SVM methods are still applicable.     

Side-Channel Information Characterisation Based on Cascade-Forward Back-Propagation Neural Network

Traditional cryptanalysis assumes that an adversary only has access to input and output pairs, but has no knowledge about internal states of the device. However, the advent of side-channel analysis showed that a cryptographic device can leak critical information. In this circumstance, Machine learning is known as a powerful and promising method of analysing of side-channel information. In this paper, an experimental investigation on a FPGA implementation of elliptic curve cryptography (ECC) was conducted to explore the efficiency of side-channel information characterisation based on machine learning techniques. In this work, machine learning is used in terms of principal component analysis (PCA) for the preprocessing stage and a Cascade-Forward Back-Propagation Neural Network (CFBP) as a multi-class classifier. The experimental results show that CFBP can be a promising approach in characterisation of side-channel information.     

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.     

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude- and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.     

Adaptive VM Management with Two Phase Power Consumption Cost Models in Cloud Datacenter

As cloud computing models have evolved from clusters to large-scale data centers, reducing the energy consumption, which is a large part of the overall operating expense of data centers, has received much attention lately. From a cluster-level viewpoint, the most popular method for an energy efficient cloud is Dynamic Right Sizing (DRS), which turns off idle servers that do not have any virtual resources running. To maximize the energy efficiency with DRS, one of the primary adaptive resource management strategies is a Virtual Machine (VM) migration which consolidates VM instances into as few servers as possible. In this paper, we propose a Two Phase based Adaptive Resource Management (TP-ARM) scheme that migrates VM instances from under-utilized servers that are supposed to be turned off to sustainable ones based on their monitored resource utilizations in real time. In addition, we designed a Self-Adjusting Workload Prediction (SAWP) method to improve the forecasting accuracy of resource utilization even under irregular demand patterns. From the experimental results using real cloud servers, we show that our proposed schemes provide the superior performance of energy consumption, resource utilization and job completion time over existing resource allocation schemes.     

Efficient Resource Management for Cloud-enabled Video Surveillance over Next Generation Network

The next generation video surveillance systems are expected to face challenges in providing computation support for an unprecedented amount of video streams from multiple video cameras in a timely and scalable fashion. Cloud computing offers huge computation resources for large-scale storage and processing on demand, which are deemed suitable for video surveillance tasks. Cloud also provides quality of service guaranteed hardware and software solutions with the virtual machine (VM) technology using a utility-like service costing model. In cloud-based video surveillance context, the resource requests to handle video surveillance tasks are translated in the form of VM resource requests, which in turn are mapped to VM resource allocation referring to physical server resources hosting the VMs. Due to the nature of video surveillance tasks, these requests are highly time-constrained, heterogeneous and dynamic in nature. Hence, it is very challenging to actually manage the cloud resources from the perspective of VM resource allocation given the stringent requirements of video surveillance tasks. This paper proposes a computation model to efficiently manage cloud resources for surveillance tasks allocation. The proposed model works on optimizing the trade-off between average service waiting time and long-term service cost, and shows that long-term service cost is inversely proportional to high and balanced utilization of cloud resources. Experiments show that our approach provides a near-optimal solution for cloud resource management when handling the heterogeneous and unpredictable video surveillance tasks dynamically over next generation network.     

Bioinspired Security Analysis of Wireless Protocols

Fraglets represent an execution model for communication protocols that resembles the chemical reactions in living organisms. The strong connection between their way of transforming and reacting and formal rewriting systems makes a fraglet program amenable to automatic verification. Grounded on past work, this paper investigates feasibility of adopting fraglets as model for specifying security protocols and analysing their properties. In particular, we give concrete sample analyses over a secure RFID protocol, showing evolution of the protocol run as chemical dynamics and simulating an adversary trying to circumvent the intended steps. The results of our analysis confirm the effectiveness of the cryptofraglets framework for the model and analysis of security properties and eventually show its potential to identify and uncover protocol flaws.     

QoS Guaranteed Resource Allocation Scheme for Cognitive Femtocells in LTE Heterogeneous Networks with Universal Frequency Reuse

In this paper, we propose a novel resource allocation scheme for co-channel interference avoidance in LTE heterogeneous networks with universal spectrum reuse where both macro users (MUs) and cognitive femto base stations (FBSs) within the same macrocell coverage can dynamically reuse whole spectrum. Specifically, resource blocks (RBs) are shared between cognitive FBSs in underlay mode while the resource sharing among FBSs and MUs is in overlay mode. The macrocell is divided into inner and outer regions with the inner region further divided into three sectors. The proposed scheme addresses co-channel interference (CCI) by employing fractional frequency reuse (FFR) for RB allocation in the outer region of the macrocell and increase the distance of users that reuse the same RB within the macrocell. Part of RBs are allocated to the outer region of the macrocell with a FFR factor of 1/3, while the remaining RBs are dynamically allocated to each sector in the inner region of macrocell based on MUs demand to efficiently utilize the available spectrum. A basic macro base station (MBS) assistance is required by the FBS in selection of suitable RB to avoid interference with MU in each sector. With the proposed solution, both macro and femto users can dynamically access the whole spectrum while having minimum bandwidth guarantee even under fully congested scenarios. Moreover, the proposed scheme practically eliminates the cross-tier interference and the CCI problem in heterogeneous network reduces to inter-femtocell interference. The throughput and outage performances of the proposed scheme are validated through extensive simulations under LTE network parameters. Simulation results show that the proposed scheme achieves a performance gain of more than 1.5 dB in terms of SINRs of both macro user and femto user compared to traditional cognitive and non-cognitive schemes without bandwidth guarantee for femtocells.     

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

A 16 MHz, highly stable voltage controlled oscillator (VCO) is reported in this paper. The proposed VCO consists of three cross-coupled RC stages, and is fully compatible with standard CMOS process. A positively biased PN junction with negative temperature coefficient is incorporated in the design to compensate frequency drift. In addition, a delay locked loop (DLL) directly following the VCO is utilized to further improve the output stability caused by temperature variations. The designed circuit was implemented using CMOS 0.18 μm technology, and was validated through experiments. Measurement results show that the DLL-assisted VCO output variation across the 25~120 °C temperature range is less than 0.56 %, corresponding to 59.2 ppm/°C. It also shows that the output standard deviation of the DLL-assisted VCO is only 6.816 KHz, ~ 16.6 % better compared with the same VCO without DLL’s assistance.     

SPSIC: Semi-Physical Simulation for IoT Clouds

Recent years have witnessed various successful demonstrations of the emerging IoT technologies, while the researchers still need to face a lot of technological challenges. It is necessary to verify and evaluate the relevant theories and calculations before the application of IoT, and that is why building a simulation platform for the IoT becomes so important, especially for a large scale IoT to meet the requirement of a scale perception in a large scope. The IoT which always contains a complicated network and communication system has made the network simulation software OPNET Modeler to be a good choice for it. Moreover, the IoT has transfer all kinds of “objects” that humans need into the form of data by various sensing equipment and intelligent devices, and those data will be stored, analyzed and processed by cloud computing finally. The paper presents an innovative method to establish an intelligent, independent and expandable data driven IoT service platform by OPNET’s Semi-Physical Simulation to combine the simulated network for IoT with the real Cloud computing(SPSIC) which applies real network to achieve the long-term surveillance, management, sharing and analysis of the collected data at any time.