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61.
Shang‐Sen Chi Yongchang Liu Wei‐Li Song Li‐Zhen Fan Qiang Zhang 《Advanced functional materials》2017,27(24)
Lithium metal is considered a “Holy Grail” of anode materials for high‐energy‐density batteries. However, both dendritic lithium deposition and infinity dimension change during long‐term cycling have extremely restricted its practical applications for energy storage devices. Here, a thermal infusion strategy for prestoring lithium into a stable nickel foam host is demonstrated and a composite anode is achieved. In comparison with the bare lithium, the composite anode exhibits stable voltage profiles (200 mV at 5.0 mA cm?2) with a small hysteresis beyond 100 cycles in carbonate‐based electrolyte, as well as high rate capability, significantly reduced interfacial resistance, and small polarization in a full‐cell battery with Li4Ti5O12 or LiFePO4 as counter electrode. More importantly, in addition to the fact that lithium is successfully confined in the metallic nickel foam host, uniform lithium plating/stripping is achieved with a low dimension change (merely ≈3.1%) and effective inhibition of dendrite formation. The mechanism for uniform lithium stripping/plating behavior is explained based on a surface energy model. 相似文献
62.
为降低TDDI产品Lead Open型线不良发生率,本文对Lead Open的发生机理进行了研究及改善验证。对TDDI产品生产数据进行了对比,对Mo-Al-Mo结构的SD膜层进行研究,根据以上结果确定改善方案并投入验证。首先,明确了Lead Open发生率与Delay Time的关系。接着,对SD膜层的微观结构进行了表征。然后,根据膜层结构和不同金属的电化学特征,建立了SD膜层电偶腐蚀模型。分析表明:Mo、Al两种金属间存在1.47V的电极电位差,具有很强的电偶腐蚀倾向性,且表层Mo中存在10nm级别的贯穿性孔洞,直径为0.4nm的水分子可轻易渗入,进而引发电偶腐蚀。表层Mo厚度增加25%后,其腐蚀速度较量产条件降低30%,Lead Open发生率降低1.4个百分点,维持在0.1%的较低水平,满足TDDI产品量产对该类不良发生率的要求。 相似文献
63.
以1280×1024红外焦平面探测器为例,利用三维可视化实体模拟软件建立了包含冷指部件、陶瓷框架、探测器芯片的三维模型,并利用ANSYS仿真软件对模型(仅球形冷台结构与常规冷台不同,其余零件均相同)进行了仿真对比.研究结果表明,球形冷台结构通过增加冷台与制冷机接触面的面积可以实现更低的芯片热应力以及更小的芯片热变形,进... 相似文献
64.
Bibhash Sen Rijoy Mukherjee Kumar Mohit Biplab K. Sikdar 《International Journal of Electronics》2013,100(8):1285-1297
The emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis. 相似文献
65.
Avishek Adhikary Pritin Sen Siddharha Sen Karabi Biswas 《Circuits, Systems, and Signal Processing》2016,35(6):1909-1932
A fractor is a simple fractional-order system. Its transfer function is \(1/Fs^{\alpha }\); the coefficient, F, is called the fractance, and \(\alpha \) is called the exponent of the fractor. This paper presents how a fractor can be realized, using RC ladder circuit, meeting the predefined specifications on both F and \(\alpha \). Besides, commonly reported fractors have \(\alpha \) between 0 and 1. So, their constant phase angles (CPA) are always restricted between \(0^{\circ }\) and \(-90^{\circ }\). This work has employed GIC topology to realize fractors from any of the four quadrants, which means fractors with \(\alpha \) between \(-\)2 and +2. Hence, one can achieve any desired CPA between \(+180^{\circ }\) and \(-180^{\circ }\). The paper also exhibits how these GIC parameters can be used to tune the fractance of emulated fractors in real time, thus realizing dynamic fractors. In this work, a number of fractors are developed as per proposed technique, their impedance characteristics are studied, and fractance values are tuned experimentally. 相似文献
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67.
对Si(111)衬底上GaN外延材料的应力随着低温AlN插入层数的变化进行了分析研究。通过喇曼散射谱在高频E2(TO)模式下的测试分析发现,随着低温AlN插入层数的增加,GaN材料的E2(TO)峰位逐渐接近体GaN材料的E2(TO)峰位(无应力体GaN材料的E2(TO)峰位为568cm-1),计算得出GaN材料的应力从1.09GPa减小到0.42GPa。同时,使用室温光荧光谱进行了分析验证。结果表明,Si衬底上GaN外延材料受到的是张应力,通过低温AlN插入层技术可以有效降低GaN材料的应力,并且最终实现了表面光亮的厚层无裂纹GaN材料。 相似文献
68.
Sen P. Sarkar S. Dawn D. Pinel S. Laskar J. 《Microwave and Wireless Components Letters, IEEE》2008,18(2):139-141
This letter presents the design and implementation of the largest reported bandwidth of a 60 GHz up/down converter with an integrated voltage controlled oscillator (VCO) in a low-cost 0.18 mum silicon-germanium process. The up/down conversion is achieved using the 2X sub-harmonic passive mixing with anti-parallel diode pairs. A 30 GHz cross-coupled VCO is designed, optimized and integrated with the sub-harmonic mixer through a cascode amplifier to meet the local oscillator power requirements. The fully integrated chip takes only 1.5 mm2 of silicon die area and consumes only 40 mW of dc power for a measured conversion loss of 12 dB at 61.5 GHz. The integrated up/down converter is measured to have greater than 9 GHz double-sided 3-dB RF bandwidth suitable for wideband high data-rate WPAN transceiver requirements. The VCO and VCO-amplifier test structures are separately fabricated and measured to have a phase noise as low as -105 dBc/Hz at 1 MHz offset with a tuning range of 2.3 GHz. 相似文献
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