Cooperative Communications in Resource-Constrained Wireless Networks

Cooperative communications have been proposed to exploit the spatial diversity gains inherent in multiuser wireless systems without the need of multiple antennas at each node. This is achieved by having the users relay each others messages and thus forming multiple transmission paths to the destination. In resource constrained networks, such as wireless sensor networks, the advantages of cooperation can be further exploited by optimally allocating the energy and bandwidth resources among users based on the available channel state information (CSI) at each node. In the first part of this article, we provide a tutorial survey on various power allocation strategies for cooperative networks based on different cooperation strategies, optimizing criteria, and CSI assumptions. In the second part, we identify the similarities between cooperative networks and several sensor network applications that utilize collaboration among distributed sensors to achieve the system goal. These applications include decentralized detection/estimation and data gathering. The techniques developed in cooperative communications can be used to solve many sensor network problems     

High-speed Modulation of InGaAs: Sb-GaAs-GaAsP quantum-well vertical-cavity surface-emitting lasers with 1.27-/spl mu/m emission wavelength

1.27-/spl mu/m InGaAs: Sb-GaAs-GaAsP vertical-cavity surface-emitting lasers (VCSELs) were grown by metal-organic chemical vapor deposition and exhibited excellent performance and temperature stability. The threshold current changes from 1.8 to 1.1 mA and the slope efficiency falls less than /spl sim/35% as the temperature raised from room temperature to 70/spl deg/C. With a bias current of only 5 mA, the 3-dB modulation frequency response was measured to be 8.36 GHz, which is appropriate for 10-Gb/s operation. The maximal bandwidth is measured to be 10.7 GHz with modulation current efficiency factor (MCEF) of /spl sim/5.25 GHz/(mA)/sup 1/2/. These VCSELs also demonstrate high-speed modulation up to 10 Gb/s from 25/spl deg/C to 70/spl deg/C.     

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-/spl mu/m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 /spl plusmn/ 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 /spl plusmn/ 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.     

A robust classification procedure based on mixture classifiers and nonparametric weighted feature extraction

There are many factors to consider in carrying out a hyperspectral data classification. Perhaps chief among them are class training sample size, dimensionality, and distribution separability. The intent of this study is to design a classification procedure that is robust and maximally effective, but which provides the analyst with significant assists, thus simplifying the analyst's task. The result is a quadratic mixture classifier based on Mixed-LOOC2 regularized discriminant analysis and nonparametric weighted feature extraction. This procedure has the advantage of providing improved classification accuracy compared to typical previous methods but requires minimal need to consider the factors mentioned above. Experimental results demonstrating these properties are presented.     

几种盲均衡算法的原理与仿真试验研究

介绍了几种恒模算法的改进算法。计算机仿真的结果表明,与恒模算法相比,多模算法和构造函数算法有较小的剩余误差和码间串扰以及更稳定的收敛效果。而构造函数算法,修正恒模算法和修正多模算法則克服了信道传输引起的相位模糊(相位偏移)。     

基于CH365芯片的PCI总线接口卡的设计与实现

PCI总线是先进的高性能32/64位局部总线,是应用最广泛的微机总线标准之一。讨论了以CH365作为接口芯片的PCI总线接口卡的设计方法,并给出了一个ISA总线接口卡快速改造为PCI总线接口卡的实例。在设计中使用了CH365芯片特有的本地硬件地址请求功能及双口RAM读写的仲裁技术。设计的PCI接口板实现了预定的功能,具有较强的实用性和较高的市场推广价值。     

Performance evaluation of random power capture on mobile communications

Power assignment schemes are man‐made methods to enhance the capture effect of radio communications. In a previous study, Wen and Yang investigated the combined capture effect of the fixed power assignment scheme, Rayleigh fading, and near–far effect on the performance of packet radios. The performance analysis was limited to an infinite population environment. This assumption is reasonable for a conventional packet radio system with a vast service area. However, for a cellular mobile system, a finite population model should be used. In this paper, we analyse the combined natural and man‐made capture effect on the performance of a cellular system with finite population in each cell. A random power assignment scheme is adopted to produce the man‐made capture. The system throughput and delay are carried out by a Markov model. Some numerical calculations are used to demonstrate the degree of performance improvement. Copyright © 2001 John Wiley & Sons, Ltd.     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Deep submicrometer double-gate fully-depleted SOI PMOS devices: aconcise short-channel effect threshold voltage model using a quasi-2Dapproach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices     

An Assessment of Testing-Effort Dependent Software Reliability Growth Models

Over the last several decades, many Software Reliability Growth Models (SRGM) have been developed to greatly facilitate engineers and managers in tracking and measuring the growth of reliability as software is being improved. However, some research work indicates that the delayed S-shaped model may not fit the software failure data well when the testing-effort spent on fault detection is not a constant. Thus, in this paper, we first review the logistic testing-effort function that can be used to describe the amount of testing-effort spent on software testing. We describe how to incorporate the logistic testing-effort function into both exponential-type, and S-shaped software reliability models. The proposed models are also discussed under both ideal, and imperfect debugging conditions. Results from applying the proposed models to two real data sets are discussed, and compared with other traditional SRGM to show that the proposed models can give better predictions, and that the logistic testing-effort function is suitable for incorporating directly into both exponential-type, and S-shaped software reliability models