Temperature-controlled and constant-power radio-frequency ablation: what affects lesion growth?

Radio-frequency (RF) catheter ablation is the primary interventional therapy for the treatment of many cardiac tachyarrhythmias. Three-dimensional finite element analysis of constant-power (CPRFA) and temperature-controlled RF ablation (TCRFA) of the endocardium is performed. The objectives are to study: 1) the lesion growth with time and 2) the effect of ground electrode location on lesion dimensions and ablation efficiency. The results indicate that: a) for TCRFA: i) lesion growth was fastest during the first 20 s, subsequently the lesion growth slowed reaching a steady state after 100 s, ii) positioning the ground electrode directly opposite the catheter tip (optimal) produced a larger lesion, and iii) a constant tip temperature maintained a constant maximum tissue temperature; b) for CPRFA: i) the lesion growth was fastest during the first 20 s and then the lesion growth slowed; however, the lesion size did not reach steady state even after 600 s suggesting that longer durations of energy delivery may result in wider and deeper lesions, ii) the temperature-dependent electrical conductivity of the tissue is responsible for this continuous lesion growth, and iii) an optimal ground electrode location resulted in a slightly larger lesion and higher ablation efficiency.     

The effect of deterministic spatial variations in retrograde wellimplants on shallow trench isolation for sub-0.18 μm CMOS technology

The high energy retrograde well implants for sub-0.18 microns CMOS are done at a normal or near normal incidence to minimize the shadowing due to the thick photoresist edges. The endstation geometry in a high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively impact device performance. We show that the spatial variations can have significant impact on shallow trench isolation (STI), by causing in a deterministic pattern the failure of STI devices on a wafer. These spatial variations are important and need to be taken into consideration for STI design     

A single-stage zero-voltage zero-current-switched full-bridge DCpower supply with extended load power range

A single-stage power-factor-corrected pulsewidth modulation power converter with extended load power range is presented. The topology is based on a zero-voltage zero-current-switched full-bridge (ZVZCS-FB) inverter. Steady-state analysis of the topology shows that by operating the LC load filter in discontinuous mode, the DC-link voltage remains bounded and independent of the load level. Therefore, the load power range can be further expanded, including the no-load operating condition. The analysis also shows that the extension of the load power range is achieved without any penalty in: (1) the input power factor (due to the input current waveshaping feature); (2) the power converter efficiency (due to ZVZCS and the single-stage features); and (3) the load voltage quality (due to the high bandwidth of the phase control loop). Simulated and experimental results are included to show the feasibility of the proposed scheme     

A source degenerated LC quadrature VCO (SD-QVCO) using 0.18-μm SiGe BiCMOS

This letter presents a fully integrated BiCMOS quadrature voltage-controlled oscillator (QVCO). The QVCO consists of two nMOSFET cross-coupled oscillator stacked in series with source degenerated HBT transistors. SiGe HBT introduces low flicker noise compared to CMOS devices. To generate quadrature phase signals with strong coupling strength, the proposed design uses two MOS-coupled LC-tank cores instead of passive device-coupled cores. This source degeneration topology can improve the phase noise performance of the QVCO as compared to the sub-VCO. The proposed QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, can generate quadrature signals in the frequency range of 4.52–5.05 GHz with core power consumption of 5.76 mW at the dc bias of 1.8 V. At 4.53 GHz, phase noise at 1 MHz offset is ?124.52 dBc/Hz. The die area of the fabricated prototype is 0.453 × 0.898 mm².     

Adaptively Grouped Multilevel Space–Time Trellis Codes Combined with Beamforming and Component Code Selection

The performance of adaptively grouped multilevel space–time trellis codes (AGMLSTTCs) is limited due to predefined component space–time trellis codes (STTCs) used in multilevel coding and lack of beamforming. In this paper, we present improvement in performance of AGMLSTTCs by combining beamforming and dynamic selection of component STTCs with AGMLSTTCs to design new codes henceforth referred to as weighted adaptively grouped multilevel dynamic space–time trellis codes. The channel state information at transmitter (CSI) is used to select a code set having different sets of generator sequences. The selected code set is used for generating dynamic STTCs (DSTTCs). The DSTTCs are used as component codes in multilevel coding. We use a single full-diversity DSTTC at some initial levels and multiple DSTTCs at some later levels. The single full diversity DSTTC at each initial level spans all transmit antennas and the DSTTC at each later level spans a group of transmit antennas. The CSI is further used to provide a beam forming scheme by properly weighting transmitted signals. Weights are selected that based on CSI at transmitter. The simulation results show that AGMLSTTCs combined with beamforming and DSTTCs provide significant improved error performance over grouped multilevel space–time trellis codes and AGMLSTTCs.     

Parameters to Define the Electron Beam Trajectory of a Double-Tapered Disc-Loaded Wideband Gyro-TWT in Profiled Magnetic Field

In the method of tapering the cross section of the interaction structure for broadbanding a gyro-TWT, the different portions of the interaction length of the tapered-cross-section waveguide become effective for different frequency ranges if the magnetic field and beam parameters are profiled to maintain the condition of electron cyclotron resonance throughout the interaction length. In the present paper, the study of profiling the magnetic field and beam parameters in steps of the stepped analytical model of a double-tapered disc-loaded circular waveguide was made throughout the steps of the model. In the observed profile, the magnetic flux density in a typical step relative to its value in first-step decreases from first-step (gun-end) to end-step (collector-end) of the model considering the up-tapering schemes, in which structure parameters increase from gun-end to collector-end. Also, the transverse beam velocity in a typical step relative to its value in first-step decreases from gun-end to collector-end. However, the Larmor radius in a typical step relative to its value in first-step as well as the hollow-beam radius in a typical step relative to its value in first-step, both increase from gun-end to collector-end in the model considering the up-tapering schemes.     

Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic

This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.     

An Adaptive Prediction Strategy with Clustering in Wireless Sensor Network

In Wireless Sensor Network, sensed data reflects two types of correlations of physical attributes: spatial and temporal. In this paper, a scheme named, Adaptive Prediction Strategy with ClusTering (APSCT) is proposed. In APSCT, a data-driven clustering and grey prediction model is used to exploit both the correlations. APSCT minimizes the transmission of messages in the network. However, the use of prediction includes additional computation overhead. There is a trade-off between prediction accuracy and energy consumption in computation and communication in wireless networks. This paper also gives an approach to calculate the upper and lower bound of the prediction interval which is used to evaluate different confidence levels and provides an energy-efficient sensor environment. Simulation is carried out on real-world data collected by Intel Berkeley Lab and results are compared with existing approaches.

     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.