Labeling design documents based on operators’ consensus—A case study of robotic design

Designers usually begin with a database to look for historical design solution, available experience and techniques through design documents, when initiating a new design. This database is a collection of labeled design documents under a few of predefined categories. However, little work has been done on labeling a relatively small number of design documents for information organization, so that most of design documents in this database can be automatically categorized.This paper initiates a study on this topic and proposes a methodology in four steps: design document collection, documents labeling, finalization of documents labeling and categorization of design database. Our discussion in this paper focuses on the first three steps. The key of this method is to collect relatively small number of design documents for manual labeling operation, and unify the effective labeling results as the final labels in terms of labeling agreement analysis and text classification experiment. Then these labeled documents are utilized as training samples to construct classifiers, which can automatically give appropriate labels to each design document.With this method, design documents are labeled in terms of the consensus of operators’ understanding, and design information can be organized in a comprehensive and universally accessible way. A case study of labeling robotic design documents is used to demonstrate the proposed methodology. Experimental results show that this method can significantly benefit efficient design information search.     

Multi-party covert communication with steganography and quantum secret sharing

In this paper, we address the “multi-party covert communication”, a stronger notion of security than standard secure multi-party communication. Multi-party covert communication guarantees that the process of it cannot be observed. We propose a scheme for steganographic communication based on a channel hidden within quantum secret sharing (QSS). According to our knowledge nobody has ever raised the scheme, providing us the motivation for this work. To an outside observer, participants will engage in a typical instance of QSS, just like the others. But when the session is over, covert multi-party communication has already been done. Further analysis shows that the amount of hidden information one can acquire is 0, even if either an outside observer guesses the covert communication is carrying on or a dishonest participant is eavesdropping.     

改进的乘积合并接收机部分频带抗干扰性能分析

乘积合并接收机以其简单有效的特性在快速跳频通信系统中得到了广泛关注。对于实际应用中普遍遇到的非最坏部分频带干扰环境,传统乘积合并算法有其自身的不足。针对这种情况,提出了一种改进的乘积合并方法,它保留了传统乘积合并算法的主要特征,通过增加对各跳频信号能量差异的检测信息,改善了传统乘积合并接收机在部分频带干扰下的传输性能,仿真验证了这种改进合并方法的有效性。     

面向小型全自动生化分析仪的同步可靠的UART通信

为了在小型全自动生化分析控制系统中实现双单片机之间同步、可靠的数据传输,提出了一种基于握手等待协议的同步可靠的UART通信系统方案。采用3次等待握手协议实现通信的同步,在数据传输过程中加入同步数据改进传输应用的稳定性。目前该方案已成功应用于小型全自动生化分析仪控制系统的数据传输,运行情况良好,性能稳定可靠。     

基于高效信道化的侦察接收机设计与实现

为了解决电子侦察接收机中同时到达信号的接收问题,从传统的低通滤波器结构出发,给出了一种无盲区高效数字信道化接收模型。信道化之后进行瞬时幅度和相位差提取。通过系统仿真,验证了该信道化模型的正确性;通过搭建信道化接收机的硬件平台并对实际系统测试,验证了瞬时幅度及相位差测试的正确性。     

可重构振荡器与双频滤波器的协同设计

实现了一种可重构振荡器与双频率滤波器的协同设计模块。振荡器通过开关二极管的通断来实现频率的可重构,工作频率分别为1.1 GHz和2.0 GHz。与双频滤波器协同设计后,振荡器在两个频率上频偏1 MHz的相位噪声分别从-109.1 dBc/Hz和-112.9 dBc/Hz改善为-125.6 dBc/Hz和-127.9 dBc/Hz,二次谐波抑制分别由协同设计之前的-25 dB和-10 dB改善为-44 dB和-55 dB。     

基于C8051F120和CPLD的多功能望远镜控制系统设计

基于C8051F120和大规模CPLD(EPM570T144)设计的多功能望远镜大型转台两轴控制系统,包括两轴直流电机伺服控制器、GPS时统系统、增量式编码器采样读数、PWM功能模块、LCD显示功能、通信功能、AD采样功能等。功能齐全,结构紧凑,外部接口丰富且具有保护功能,可靠性高。     

基于SoPC的直流无刷电机加速度控制研究与实现

为了实现对直流无刷电机加速度的准确控制,在分析几种加速度控制方案的基础上,提出了在电机加速阶段,通过在速度控制回路前向通道上加一积分环节来实现加速度控制的方案。详细介绍了该方案的原理并给出了基于SoPC技术的设计思想和实现方法。     

基于FPGA的新型高速CCD图像数据采集系统

介绍一种基于Actel公司Fusion StartKit FPGA的线阵CCD图像数据采集系统。以FPGA作为图像数据的控制和处理核心,通过采用高速A/D、异步FIFO、UART以及电平转换、放大滤波、二值化电路和光学系统实现对图像数据的信号处理,并运用Visual Studio C++和Microsoft公司的基本类库MFC实现对采集数据的显示、绘图、传输控制等。利用搭建的系统平台实现对物体尺寸的测量,通过对所得的数据进行分析处理,明确测量的精度和可以达到的水平。对该系统在实时监控中的优点进行分析。     

H.264/AVC中CAVLC编码器的硬件设计与实现

设计了一种H.264标准的CAVLC编码器,对原有软件流程进行部分改进,提出了并行处理各编码子模块的算法结构。重点对非零系数级(level)编码模块进行优化,采用并行处理和流水线相结合的结构,减少了cavlc编码的时钟周期,提供了稳定吞吐量。采用Xilinx公司VirtexⅡ系列的xc2v250 FPGA进行实现验证,最高时钟频率可达158.1 MHz,可满足实时编码H.264高清视频要求。