Effect of linker used in D–A–π–A metal free dyes with different π-spacers for dye sensitized solar cells

Two novel D–A–π–A metal free dyes with triphenylamine as donor, dithiophene-diketo-pyrrolo-pyrrole as acceptor unit, thiophene and phenyl π-conjugated bridges and a cyanoacetic acid as electron acceptor (TDPP1 and TDPP2 were denoted for thiophene and phenyl π-conjugated bridge, respectively) have been designed and used as sensitizers for DSSCs. Incorporation of dithiophene-diketo-pyrrolo-pyrrole, reduces the band gap significantly. The influence of π-conjugated bridge on optical and electrochemical properties were investigated. Results demonstrated that the absorption band of TDPP with thiophene π-conjugated bridge has red shifted due to the enhancement of electron donating ability of π-conjugated bridge. The DSSC based on TDPP1 shows prominent power conversion efficiency about 4.81%, which is higher that for TDPP2 (3.42%). The electrochemical impedance spectroscopy analysis reveal that the charge recombination resistance at the TiO₂/dye/electrolyte interface for the DSSC based on TDPP1 is higher than that for TDPP2, which improves both J_sc and V_oc. The PCE of the DSSC based on TDPP1 is further improved up to 6.34%, when deoxycholic acid (DCA) was employed as coadsorbant.     

Exact scattering for axial incidence on an isorefractive paraboloid

The canonical solution to the problem of the scattering of a plane electromagnetic wave axially incident on the convex side of an isorefractive paraboloid is provided. The exact scattered field consists of the geometrical optics reflected field on the convex side of the paraboloid and of a transmitted plane wave on the concave side of the paraboloid     

Stress-induced effects by the anodic oxide in ridge waveguide laserdiodes

This paper studies, both theoretically and experimentally, stress-induced effects on the lateral far-field behavior for ridge-type semiconductor laser diodes where anodic oxide is used for the definition of the stripe width. These effects consist of antiguiding under the stripe region, and of two positive waveguiding features near the stripe edges. For low-threshold devices, these effects may be more important than thermal effects, depending on the stress in the oxide. They put a lower limit on the built-in index guiding to be introduced by lateral etch outside the ridge region in order to maintain fundamental mode operation for wider stripes. The magnitude of these effects may be as large as Δn_ef=1×10^-3. An analytical mathematical model is deduced for computing stresses and strains for a certain ridge-shaped interface which bounds the elastic medium     

Charge, current, and noise partitioning in MOSFET in the presence of mobility degradation

The Ward-Dutton (WD) partitioning scheme is used extensively to develop transient and high-frequency advanced compact models in MOSFET analysis. However, it remains an open question if this scheme can be used for field-dependent mobility that is enhanced in state-of-the-art submicrometer technologies. In this paper, after demonstrating that the well-known WD partitioning is indeed invalid for field-dependent mobility, the authors develop a very general partitioning strategy that can always be defined in small-signal analysis for any arbitrary velocity-field relationship. It has also been shown that for large-signal operation, the existence of a partitioning scheme can be determined by the solution of an integral equation.     

Stochastic Modeling of TCP in Networks with Abrupt Delay Variations

An analytical model of TCP (Transport Control Protocol) over an end-to-end path with random abrupt round-trip time (RTT) changes is presented. Modeling the RTT as a stochastic process, we analytically quantify and compare between the degree of degradation of the steady-state average throughput and window size due to spurious retransmissions for the different versions of TCP (Reno/NewReno versus Tahoe). The modeling methodology in this paper is used for evaluating different design alternatives for TCP for highly dynamic networks.     

Discrete Rayleigh distribution

Using a general approach for discretization of continuous life distributions in the univariate & bivariate situations, we have proposed a discrete Rayleigh distribution. This distribution has been examined in detail with respect to two measures of failure rate. Characterization results have also been studied to establish a direct link between the discrete Rayleigh distribution, and its continuous counterpart. This discretization approach not only expands the scope of reliability modeling, but also provides a method for approximating probability integrals arising out of a continuous setting. As an example, the reliability value of a complex system has been approximated. This discrete approximation in a nonnormal setting can be of practical use & importance, as it can replace the much relied upon simulation method. While the replication required is minimal, the degree of accuracy remains reasonable for our suggested method when compared with the simulation method.     

On fast evaluation of bivariate polynomials at equispaced arguments

The initial value problem arising in the recursive evaluation of a 2D polynomial at equispaced points is treated in detail; the results facilitate efficient implementation of Bose's recursive algorithm. The computational complexity is compared with that involved in a direct computation, and some general observations are made for an alternative scheme proposed by X. Nie and R. Unbehauen (1989)     

Profit Aware Circuit Design Under Process Variations Considering Speed Binning

In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve economic gain of a design over its initial yield-optimized design. Finally, we present an integrated design methodology for simultaneous sizing and bin boundary determination to enhance profit under an area constraint. Experiments on a set of ISCAS'85 benchmarks show in average 19% improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds compared to a design initially optimized for 90% yield at iso-area in 70-nm bulk CMOS technology.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.