Formation of GaAsP interface layers monitored by reflectance anisotropy spectroscopy

Reflectance anisotropy spectroscopy (RAS) has been used to study As-by-P exchange during metalorganic vapor phase epitaxy. The study focuses on the processes occurring during switching from GaAs to GaInP, especially the effect of purging PH₃ over a GaAs surface. GaAsP/GaAs superlattices of different periodicity were grown and the P-content was determined by high-resolution x-ray diffraction and correlated to the RAS spectra. From the temperature dependence of the P-content, an activation energy of 0.56 eV was estimated for the incorporation mechanism. In addition to the insights into the processes at mixed group-V heterointerfaces, our study demonstrates the reproducibility of RAS transients that thus can be used for process monitoring.     

Cumulated interference power and bit‐error‐rates in mobile packet radio

In this paper we determine the probability distribution function of cumulated instantaneous interference power in a mobile radio network, when the positions of interfering stations are distributed according to a one‐ or two‐dimensional Poisson point process, truncated at a finite horizon. The influences of Rice and Rayleigh fading, lognormal shadowing, near far effect and capture are taken into account. From the resulting distribution the probability of successful transmission and corresponding bit‐error‐rates are derived. This revised version was published online in July 2006 with corrections to the Cover Date.     

Progress in Low-temperature Surface Passivation of Silicon Solar Cells using Remote-plasma Silicon Nitride

Using a remote-plasma technique as opposed to the conventional direct-plasma technique, significant progress has been obtained at ISFH in the area of low-temperature surface passivation of p-type crystalline silicon solar cells by means of silicon nitride (SiN) films fabricated at 350–400°C in a plasma-enhanced chemical vapour deposition system. If applied to the rear surface of the low-resistivity p-type substrates, the remote-plasma SiN films provide outstanding surface recombination velocities (SRVs) as low as 4 cm s⁻¹, which is by a clear margin the lowest value ever obtained on a low-resistivity p-Si wafer passivated by a solid film, including highest quality thermal oxides. Compared to direct-plasma SiN films or thermally grown oxides, the remote-plasma films not only provide significantly better SRVs on low-resistivity p-silicon wafers, but also an enormously improved stability against ultraviolet (UV) light. The potential of these remote-plasma silicon nitride films for silicon solar cell applications is further increased by the fact that they provide a surface passivation on phosphorus-diffused emitters which is comparable to high-quality thermal oxides. Furthermore, if combined with a thermal oxide and a caesium treatment, the films induce a UV-stable inversion-layer emitter of outstanding electronic quality. Due to the low deposition temperature and the high refraction index, these remote-plasma SiN films act as highly efficient surface-passivating antireflection coatings. Application of these films to cost-effective silicon solar cell designs presently under development at ISFH turned out to be most successful, as demonstrated by diffused p-n junction cells with efficiencies above 19%, by bifacial p-n junction cells with front and rear efficiencies above 18%, by mask-free evaporated p-n junction cells with efficiencies above 18% and by MIS inversion-layer cells with a new record efficiency of above 17%. All cells are found to be stable during a UV test corresponding to more than 4 years of glass-encapsulated outdoor operation. © 1997 John Wiley & Sons, Ltd.     

High‐Throughput Fabrication of Au–Cu Nanoparticle Libraries by Combinatorial Sputtering in Ionic Liquids

Materials libraries of binary alloy nanoparticles (NPs) are synthesized by combinatorial co‐sputter deposition of Cu and Au into the ionic liquid (IL) 1‐butyl‐3‐methylimidazolium bis(trifluoromethylsulfonyl)imide ([C₁C₄im][Tf₂N]), which is contained in a micromachined cavity array substrate. The resulting NPs and NP‐suspensions are investigated by transmission electron microscopy (TEM), X‐ray diffraction (XRD), UV‐Vis measurements (UV‐Vis), and attenuated total reflection Fourier transformed infrared (ATR‐FTIR) spectroscopy. Whereas the NPs can be directly observed in the IL using TEM, for XRD measurements the NP concentration is too low to lead to satisfactory results. Thus, a new NP isolation process involving capping agents is developed which enables separation of NPs from the IL without changing their size, morphology, composition, and state of aggregation. The results of the NP characterization show that next to the unary Cu and Au NPs, both stoichiometric and non‐stoichiometric Cu–Au NPs smaller than 7 nm can be readily obtained. Whereas the size and shape of the alloy NPs change with alloy composition, for a fixed composition the NPs have a small size distribution. The measured lattice constants of all capped NPs show unexpected increased values, which could be related to the NP/surfactant interactions.     

Classical Capacity of Classical-Quantum Arbitrarily Varying Channels

We prove that the average error classical capacity C(W) of a classicalquantum arbitrarily varying channel (cq-AVC) W equals 0 or else the random code capacity C (Ahlswede's dichotomy). We also establish a necessary and sufficient condition for C(W)>0     

Reverse short channel effects in high-k gated nMOSFETs

Anomalous threshold voltage roll-up behavior, commonly referred as reverse short channel effect (RSCE), has been observed in high-k (HfO₂ on SiON buffer, Al₂O₃ on SiON buffer) gated submicron nMOSFETs, while the SiO₂ or SiON control samples show normal short channel effect (SCE) behavior. The possible causes such as inhomogeneous channel doping profile and gate oxide thickness variation near S/D ends have been ruled out. The results indicate that interface trap density that dependents on channel length is the main cause of the RSCE observed here. In addition, oxide charge also plays a role.     

Gallium gradients in Cu(In,Ga)Se2 thin‐film solar cells

The gallium gradient in Cu(In,Ga)Se₂ (CIGS) layers, which forms during the two industrially relevant deposition routes, the sequential and co‐evaporation processes, plays a key role in the device performance of CIGS thin‐film modules. In this contribution, we present a comprehensive study on the formation, nature, and consequences of gallium gradients in CIGS solar cells. The formation of gallium gradients is analyzed in real time during a rapid selenization process by in situ X‐ray measurements. In addition, the gallium grading of a CIGS layer grown with an in‐line co‐evaporation process is analyzed by means of depth profiling with mass spectrometry. This gallium gradient of a real solar cell served as input data for device simulations. Depth‐dependent occurrence of lateral inhomogeneities on the µm scale in CIGS deposited by the co‐evaporation process was investigated by highly spatially resolved luminescence measurements on etched CIGS samples, which revealed a dependence of the optical bandgap, the quasi‐Fermi level splitting, transition levels, and the vertical gallium gradient. Transmission electron microscopy analyses of CIGS cross‐sections point to a difference in gallium content in the near surface region of neighboring grains. Migration barriers for a copper‐vacancy‐mediated indium and gallium diffusion in CuInSe₂ and CuGaSe₂ were calculated using density functional theory. The migration barrier for the In_Cu antisite in CuGaSe₂ is significantly lower compared with the Ga_Cu antisite in CuInSe₂, which is in accordance with the experimentally observed Ga gradients in CIGS layers grown by co‐evaporation and selenization processes. Copyright © 2014 John Wiley & Sons, Ltd.     

Two-channel switched reluctance starter/generator results

Measured data and simulation results for a two-channel experimental switched-reluctance-motor (SRM)-based aircraft engine starter/generator system are presented. The two channels of the system provide power to two separate and independent loads. The results presented document the performance capability of this system with both channels operating simultaneously. Both measured and predicted system performance are presented and compared. In addition, operating characteristics that are unique to this SRM-based system are described. Of particular interest are the interactions between the two separate channels when one channel experiences a load transient and the other channel does not. The source of channel interactions is described, and measured data is provided. The issue of clearing load faults is also addressed. Design results for adding this capability to the experimental system are described     

Finite element simulation of package stress in transfer molded MEMS pressure sensors

The goal of this paper is to investigate the effect of residual packaging stress resulting from transfer molding of a micro electro mechanical system pressure sensor. A model of a silicon diaphragm micro electro mechanical system pressure sensor geometry was used to simulate the stresses developed during the molding process. The analyses were carried out with an assumption that the epoxy molding compound was a temperature dependent elastic material. Finite element analysis was used to calculate the residual packaging stress. The stress values were used to obtain the electrical output signal and sensitivity of the packaged sensor. In this way, a direct link was established between package stress and device performance.The calculated output signal and sensitivity were compared with experimental data to verify the simulated stress and hence determine the effect of the packaging process on the pressure sensor. Four different service temperatures were considered to examine the temperature effects on the output signal and the sensitivity for the packaged sensor.     

Interleaving on Parallel DSP Architectures

Today's communications systems especially in the field of wireless communications rely on many different algorithms to provide applications with constantly increasing data rates and higher quality. This development combined with the wireless channel characteristics as well as the invention of turbo codes has particularly increased the importance of interleaver algorithms. In this paper, we demonstrate the feasibility to exploit the hardware parallelism in order to accelerate the interleaving procedure. Based on a heuristic algorithm, the possible speedup for different interleavers as a function of the degree of parallelism of the hardware is presented. The parallelization is generic in the sense that the assumed underlying hardware is based on a parallel datapath DSP architecture and therefore provides the flexibility of software solutions.